ADBMS2950BCCSZ datasheet(46/97 Pages) AD

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ADBMS2950B

Data Sheet

Rev. 0 | Page 46 of 97

PWM2 Overcurrent Output Mode

The PWM2 mode is optimized for communicating the

overcurrent condition to an external microcontroller, which

features a timer or Capture-Compare Unit (CAPCOM). It

provides more detailed information than the PWM1 Mode. The

microcontroller is informed whether one, two, or all the three

OCxADCs report an overcurrent event. The microcontroller is

also made aware of whether any of the overcurrent channels

reports an overcurrent while diagnostics are performed or while

faults are pending.

A duty cycle of 50% indicates a healthy device and no

overcurrent. Greater duty cycles indicate the overcurrent

detection. Lower duty cycles indicate pending faults or ongoing

diagnostics. Table 61 shows all duty-cycle encodings. The

microcontroller can further deglitch events for more

conservative ignition because the overcurrent events are not

latched inside the IC.

When an overcurrent event, a fault or a diagnostic case is

detected, the ongoing PWM period completes, and the new

duty cycle is applied from the next period onwards.

Table 61. PWM2 Overcurrent Output Mode Duty-Cycle Coding for OCAX = 0, OCBX = 0

Duty Cycle

Description

0% - High-Z

OCx pins in high impedance state after reset and whenever OCEN = 0.

12.5%

Detection of any SPF, which is a DFI for OC1-2-3 and not executing diagnostic (for OC).

25%

Executing diagnostic (for OC).

37.5%

Detection of any SPF, which is a DFI for OC1-2-3 and when executing diagnostic (for OC).

50%

No fault, no diagnostic, no overcurrent.

62.5%

1 OCxADC threshold violation is occurring.

75%

2 OCxADC threshold violations are occurring.

87.5%

3 OCxADC threshold violations are occurring.

Overcurrent Threshold Considerations

The overcurrent ADCs (OCxADC) convert the average input

signal over the conversion window length, which is about 62 µs.

This equals the integral of the input signal waveform over the

conversion window. As a result, short pulses higher than the

threshold setting can result in an offending or a non-offending

threshold comparison, which depends on the area of the

waveform.

Figure 38. Example of Offending Overcurrent Threshold Case

Figure 38 shows an example of an offending condition. The

input signal has a baseline of 90 mV with a pulse of 200 mVpp

that lasts 10% of the conversion window. Effectively, the average

signal becomes 0.9 × 90 mV + 0.1 × 200 mV resulting in

101 mV, which is above the programmed threshold of 100 mV

shown by the OCxTH line in Figure 38.

Figure 39. Example of Non-Offending Overcurrent Threshold Case

Figure 39 shows an example of a non-offending condition. The

input signal has a baseline of 100 mV with two 0 mV low pulses

that last 6.5% of the conversion window each. Effectively, the

average signal becomes 0.87 × 100 mV + 0.13 × 0 mV resulting

in 87 mV, which is below the programmed threshold of 90 mV

indicated by the OCxTH line in the figure. The external RC

filter further averages out signal peaks before they are sensed by

the input pins, helping to deglitch noise or short spikes at the

inputs.

Controlling the Overcurrent Detection

To prevent an unintended activation of the OCA and OCB pins,

the overcurrent configuration bits OC1TH to OC3TH,

OCDGT, OCMODE, OCAX, OCBX, OCDP, OCOD, and

OC1GC to OC3GC are latched with the rising edge of OCEN

(transition of the bit from 0 to 1). Once the OCEN bit is set, the

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