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ADBMS2950BCCSZ Datasheet(PDF) 63 Page - Analog Devices |
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ADBMS2950BCCSZ Datasheet(HTML) 63 Page - Analog Devices |
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63 / 97 page  Data Sheet ADBMS2950B Rev. 0 | Page 63 of 97 Figure 44. STCOMM Timing Diagram for an SPI Controller Figure 45. STCOMM Timing Diagram for an I2C Controller I2C/SPI Controller Timing The timing of the I2C or SPI controller is set by the timing of the communication at the primary SPI interface of the ADBMS2950B. Table 85 shows the SPI controller timing specifications. Table 86 shows the I2C controller timing relationship to the primary SPI clock. Table 85. SPI Controller Timing SPI Controller Parameter Timing Relationship to Primary SPI Timing Specifications at tCLK = 0.5 µs SDIOM, SDOM Valid to SCKM Rising Setup t3 Min 100 ns SDIO Valid from SCKM Rising Hold tCLK + t14 Min 0.53 µs SCKM Low tCLK Min 0.5 µs SCKM High tCLK Min 0.5 µs SCKM Period (SCKM Low + SCKM High) 2 × tCLK Min 1 µs CSBM Pulse Width 3 × tCLK Min 1.5 µs SCKM Rising to CSBM Rising 5 × tCLK + t14 Min 2.53 µs CSBM Falling to SCKM Falling t3 Min 100 ns |
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