ARMV4T datasheet(8/30 Pages) ACTEL

8 / 30 page

CoreMP7

v2.6

Link Register

(LR).

with Link (BL) instruction is executed.

At all other times, you can treat r14 as a general-

purpose register.

The

corresponding

banked

registers—r14_svc,

r14_irq, r14_fiq, r14_abt, and r14_und—are similarly

used to hold the return values of r15 when interrupts

and exceptions arise, or when BL instructions are

executed within interrupt or exception routines.

Program Counter

In ARM state, bits [1:0] of r15 are zero. Bits [31:2]

contain the PC.

In Thumb state, bit [0] is zero. Bits [31:1] contain the PC.

In privileged modes, another register, the Saved Program

Status Register (SPSR), is accessible. This contains the

condition code flags, and the mode bits saved as a result

of the exception that caused entry to the current mode.

Figure 4 shows the ARM state registers.

Figure 4 •

CoreMP7 Register Organization in the ARM State

ARM State General Registers and Program Counter

ARM State Program Status Registers

r10

r11

r12

r13

r14

r15 (PC)

= banked register

CPSR

r8_fiq

r9_fiq

r10_fiq

r11_fiq

r12_fiq

r13_fiq

r14_fiq

r15 (PC)

CPSR

SPSR_fiq

r10

r11

r12

r13_svc

r14_svc

r15 (PC)

CPSR

SPSR_svc

r10

r11

r12

r13_abt

r14_abt

r15 (PC)

CPSR

SPSR_abt

r10

r11

r12

r13_irq

r14_irq

r15 (PC)

CPSR

SPSR_irq

r10

r11

r12

r13_und

r14_und

r15 (PC)

CPSR

SPSR_und

System and User

FIQ

Supervisor

Abort

IRQ

Undefined

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