CoreMP7

v2.6

9

The Thumb State Register Set

The Thumb state register set is a subset of the ARM state set. The programmer has direct access to the following:

•

Eight general registers, r0–r7

•The PC

•

A Stack Pointer (SP)

•

A Link Register (LR)

•

The CPSR

There are banked SPs, LRs, and SPSRs for each privileged mode. The Thumb state register set is shown in Figure 5.

Figure 5 •

CoreMP7 Thumb State Registers

Thumb State General Registers and Program Counter

Thumb State Program Status Registers

r0

r1

r2

r3

r4

r5

r6

r7

SP

LR

PC

r0

r1

r2

r3

r4

r5

r6

r7

SP_fiq

LR_fiq

PC

r0

r1

r2

r3

r4

r5

r6

r7

SP_svc

LR_svc

PC

r0

r1

r2

r3

r4

r5

r6

r7

SP_abt

LR_abt

PC

r0

r1

r2

r3

r4

r5

r6

r7

SP_irq

LR_irq

PC

r0

r1

r2

r3

r4

r5

r6

r7

SP_und

LR_und

PC

= banked register

CPSR

CPSR

SPSR_fiq

CPSR

SPSR_svc

CPSR

SPSR_abt

CPSR

SPSR_irq

CPSR

SPSR_und

System and User

FIQ

Supervisor

Abort

IRQ

Undefined