ARMV4T datasheet(23/30 Pages) ACTEL

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CoreMP7

v2.6

Debug

The ARM Debug Architecture uses a protocol converter

box to allow the debugger to talk via a Joint Test Action

Group (JTAG) port directly to the core. In effect, the scan

chains in the core that are required for test are re-used

for debugging.

The

architecture

uses

the

scan

chains

insert

instructions directly in to the ARM core. The instructions

are executed on the core and, depending on the type of

instruction that has been inserted, the core or the system

state

can

examined,

saved,

changed.

The

architecture has the ability to execute instructions at a

slow debug speed or to execute instructions at system

speed (for example, if access to an external memory was

required).

The fact that the debugger is actually using the JTAG

scan chains to access the core is of no importance to the

user, as the front end debugger remains exactly the

same. The user could still use the debugger with a

monitor program running on the target system or with

an instruction set simulator that runs on the debugger

host. In each case the debugging environment is the

same.

The advantages of using the JTAG port are:

•

Hardware access required by a system for test is re-

used for debug.

•

Core state and system state can be examined via

the JTAG port.

•

The target system does not have to be running in

order to start debug.

A monitor program for example requires that some

target resources are running in order for the monitor

program to run.

•

Traditional

breakpoints

and

watchpoints

are

available.

•

On-chip resources can be supplemented.

•

For example, the ARM Debug Architecture uses an

on-chip macro-cell to enhance the debugging

facilities available.

tIHEXC

nFIQ, nIRQ, nRESET hold from rising CLK

–0%

tISCFG

CFGBIGEND setup to rising CLK

10%

–

tIHCFG

CFGBIGEND hold from rising CLK

–0%

tISDBGCTL

DBGBREAK, DBGEXT, DBGRQ input setup to rising CLK

10%

–

tISDBGSTAT

Debug status inputs setup to rising CLK

10%

–

tIHDBGSTAT

Debug status inputs hold from rising CLK

–0%

tOVDBGCTL

Rising CLK to debug control valid

–

40%

tOHDBCTL

Debug control hold time from rising CLK

>0%

–

tISTCLKEN

DBGTCKEN input setup to rising CLK

60%‘

–

tIHTCKEN

DBGTCKEN input hold from rising CLK

–0%

tISTCTL

DBGTDI, DBGTMS input setup to rising CLK

35%

–

tIHTCTL

DBGTDI, DBGTMS input hold from rising CLK

–0%

tOVTDO

Rising CLK to DBGTDO valid

–

20%

tOHTDO

DBGTDO hold time from rising CLK

>0%

–

tOVDBGSTAT

Rising CLK to debug status valid

40%

–

tOHDBGSTAT

Debug status hold time

>0%

–

Table 6 •

AC Timing Parameters (Continued)

Symbol

Parameter

Min

Max

Notes:

1. tIHCLKEN is 0 ns for the Core Plus Debug variant in all devices.

2. tIHCLKEN is 1 ns for the Core Only variant in all devices.

3. tIHRDATA is 0 ns for Core Plus Debug variant in all devices.

4. tIHRDATA is 1 ns for Core Only variant in all devices.

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