HCS12 datasheet(53/452 Pages) FREESCALE

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S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

4.4.3.3 Bit Condition Branches

Bit condition branch instructions read a location in memory, and branch if

the bits in that location are in a certain state. These instructions can use

direct, extended, or indexed addressing modes. Indexed operations require

varying amounts of information to determine the effective address, so

instruction length varies according to the mode used, which in turn affects

the amount of program information fetched. To shorten execution time,

these branches perform one program word fetch in anticipation of the

“taken” case. The data from this fetch is ignored in the “not-taken” case. If

the branch is taken, the CPU fetches three program word fetches at the new

address to fill the instruction queue.

4.4.3.4 Loop Primitives

The loop primitive instructions test a counter value in a register or

accumulator and branch to an address specified by a 9-bit relative offset

contained in the instruction if a specified condition is met. There are

auto-increment and auto-decrement versions of these instructions. The test

and increment/decrement operations are performed on internal CPU

registers, and require no additional program information. To shorten

execution time, these branches perform one program word fetch in

anticipation of the “taken” case. The data from this fetch is ignored if the

branch is not taken, and the CPU does one program fetch and one optional

fetch to refill the queue1. If the branch is taken, the CPU finishes refilling the

queue with two additional program word fetches at the new address.

4.4.4 Jumps

Jump (JMP) is the simplest change of flow instruction. JMP can use

extended or indexed addressing. Indexed operations require varying

amounts of information to determine the effective address, so instruction

length varies according to the mode used, which in turn affects the amount

of program information fetched. All forms of JMP perform three program

word fetches at the new address to refill the instruction queue.

1. In the original M68HC12, the implementation of these two cycles are both program word

fetches.

HCS12 Datasheet(PDF) 53 Page - Freescale Semiconductor, Inc