SPEAR1310 datasheet(56/57 Pages) STMICROELECTRONICS

56 / 57 page

Revision history

SPEAr1310

56/57

Doc ID 17528 Rev 4

Revision history

Table 3.

Document revision history

Date

Revision

Changes

4-Jun-2010

Initial release.

20-Aug-2010

Modified confidentiality level

from public to confidential.

Minor text changes.

26-Aug-2010

Modified confidentiality level from confidential to public for the announce of the

product.

2-Sep-2010

Updated information about PCIe and SATA:

– Modified the feature list in the first page.

– Modified Figure 1: SPEAr1310 system connectivity

– Modified Figure 2: SPEAr1310 block diagram of the internal connectivity

Reviewed the structure of the document.

Reviewed Chapter 8: Static RAM (SRAM)

Added Chapter 7: Reset and clock generator (RCG)

Updated Chapter 9: Multiport memory controller (MPMC)

Updated Chapter 10: Flexible static memory controller (FSMC)

Updated Chapter 12: Giga/Fast Ethernet media access controller (GMAC)

Updated Chapter 16: 32-bit PCI expansion bus

Updated Chapter 23: Universal asynchronous receiver/transmitter (UART)

Updated Chapter 30: Security co-processor (C3)

Updated Chapter 32: General purpose timer (GPT)

Updated Chapter 33: Real-time clock (RTC)

Updated Chapter 35: JPEG Codec (JPGC)

SPEAR1310 Datasheet(PDF) 56 Page - STMicroelectronics