SPEAR1310 datasheet(18/57 Pages) STMICROELECTRONICS

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Multiport memory controller (MPMC)

SPEAr1310

18/57

Doc ID 17528 Rev 4

Multiport memory controller (MPMC)

MPMC is a high performance multichannel memory controller able to support DDR2 and

DDR3 double data rate memory devices. The multiport architecture ensures that memory is

shared efficiently among different high-bandwidth client modules.

9.1

Main features

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Supports both DDR3 and DDR2 devices. Wide range of memory device cuts

supported: from 128 Mb to 4 Gb for each chip select. Two chip selects supported.

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Programmable memory datapath size of full memory 32-bit data width or half memory

16 bits data width

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Clock frequencies from 100 MHz to 533 MHz supported

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6 AXI interfaces with a data interface width of 64 bits. Each port is configured with a

thread ID of 4 bits

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Exclusive and locked accesses support Weighted Round-Robin arbitration scheme

support to ensure high memory bandwidth utilization

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DRAM command processing

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A programmable register interface to control memory device parameters and protocols

including auto pre-charge

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Full initialization of memory on memory controller reset

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Automatically maps user addresses to the DRAM memory in a contiguous block

addressing starts at user address 0 and ends at the highest available address

according to the size and number of DRAM devices present

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Fully pipelined command, read and write data interfaces to the memory controller

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Advanced bank look-ahead features for high memory throughput

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7-bit ECC functionality with single-bit and double-bit error reporting and automatic

correction of single-bit error events. Programmable reporting and correction.

Programmable removal of ECC storage

SPEAR1310 Datasheet(PDF) 18 Page - STMicroelectronics

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