OPTION_REG datasheet(97/222 Pages) MICROCHIP

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DS22331A-page 97

MCP19111

15.3.1.4

PIR2 Register

The PIR2 register contains the Peripheral Interrupt

Flag bits, as shown in Register 15-5.

Note 1: Interrupt flag bits are set when an

interrupt condition occurs, regardless of

the state of its corresponding enable bit

or the Global Enable bit, GIE of the

INTCON register. User software should

ensure the appropriate interrupt flag bits

are clear prior to enabling an interrupt.

PIR2 – PERIPHERAL INTERRUPT FLAG REGISTER 2

R/W-0

U-0

R/W-0

U-0

R/W-0

U-0

UVIF

—OCIF

OVIF

—

—VINIF

—

bit 7

bit 0

Legend:

R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

UVIF: Output undervoltage error interrupt flag bit

= Output undervoltage error has occurred

= Output undervoltage error has not occurred

bit 6

UNIMPLEMENTED: Read as '0'

bit 5

OCIF: Output overcurrent error interrupt flag bit

= Output overcurrent error has occurred

= Output overcurrent error has not occurred

bit 4

OVIF: Output overvoltage error interrupt flag bit

= Output overvoltage error has occurred

= Output overvoltage error has not occurred

bit 3-2

UNIMPLEMENTED: Read as '0'

bit 1

VINIF: VIN Status bit

= VIN is below acceptable level

= VIN is at acceptable level

bit 0

UNIMPLEMENTED: Read as '0'

TABLE 15-1:

SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

on Page

INTCON

GIE

PEIE

T0IE

INTE

IOCE

T0IF

INTF

IOCF

OPTION_REG

RAPU

INTEDG

T0CE

T0SE

PSA

PS2

PS1

PS0

PIE1

—

ADIE

BCLIE

SSPIE

—

TMR2IE

TMR1IE

PIE2

UVIE

—OCIE

OVIE

—

VINIE

—

PIR1

—

ADIF

BCLIF

SSPIF

—

TMR2IF

TMR1IF

PIR2

UVIF

—OCIF

OVIF

—

VINIF

—

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupts.

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