OPTION_REG datasheet(15/222 Pages) MICROCHIP

15 / 222 page

 2013 Microchip Technology Inc.

DS22331A-page 15

MCP19111

3.0

FUNCTIONAL DESCRIPTION

3.1

Linear Regulators

Two internal linear regulators generate two 5V rails.

One 5V rail is used to provide power for the internal

analog circuitry and is contained on-chip. The second

5V rail provides power to the internal PIC core and it is

present on the VDD pin. It is recommended that a 1 µF

capacitor be placed between VDD and PGND.

The

VDR pin provides power to the internal

synchronous MOSFET driver. VDD can be directly

connected to VDR or connected through a low-pass RC

filter to provide noise filtering. A 1 µF ceramic bypass

capacitor should be placed between VDR and PGND.

When connecting VDD to VDR, the gate drive current

required to drive the external MOSFETs must be added

to the MCP19111 quiescent current, IQ(max). This total

current must be less than the maximum current,

IDD-OUT, available from VDD that is specified in

Section 4.2 “Electrical Characteristics”.

EQUATION 3-1:

TOTAL REGULATOR

CURRENT

EQUATION 3-2:

GATE DRIVE CURRENT

Alternatively, an external regulator can be used to

power the synchronous driver. An external 5V source

can be connected to VDR. The amount of current

required from this external source can be found in

Equation 3-2. Care must be taken that the voltage

applied to VDR does not exceed the maximum ratings

found

Section 4.1

“Absolute

Maximum

Ratings (†)”.

3.2

Internal Synchronous Driver

The internal synchronous driver is capable of driving

two N-Channel MOSFETs in a synchronous rectified

buck converter topology. The gate of the floating

MOSFET is connected to the HDRV pin. The source of

this MOSFET is connected to the PHASE pin. The

HDRV pin source and sink current is configurable. By

setting the DRVSTR bit in the PE1 register, the high-

side is capable of sourcing and sinking a peak current

of 1A. By clearing this bit, the source and sink peak

current is 2A.

The MOSFET connected to the LDRV pin is not

floating. The low-side MOSFET gate is connected to

the LDRV pin and the source of this MOSFET is

connected to PGND. The drive strength of the LDRV pin

is not configurable. This pin is capable of sourcing a

peak current of 2A. The peak sink current is 4A. This

helps keep the low-side MOSFET off when the

high-side MOSFET is turning on.

3.2.1

MOSFET DRIVER DEAD TIME

The MOSFET driver dead time is defined as the time

between

one

drive

signal

going

low

and

the

complimentary drive signal going high. Refer to

Figure 6-2. The MCP19111 has the capability to adjust

both the high-side and low-side driver dead time

independently. The adjustment of the driver dead time

is controlled by the DEADCON register and is

adjustable in 4 ns increments.

3.2.2

MOSFET DRIVER CONTROL

The MCP19111 has the ability to disable the entire

synchronous driver or just one side of the synchronous

drive signal. The bits that control the MOSFET driver

can be found in the Register 8-1.

setting

ATSTCON<DRVDIS>,

the

entire

synchronous driver is disabled. The HDRV and LDRV

signals are set low and the PHASE pin is floating.

Clearing this bit allows normal operation.

OUT

–

DRIVE

EXT



Where:

-IDD-OUT is the total current available from VDD

-IQ is the device quiescent current

-IDRIVE is the current required to drive the

external MOSFETs

-IEXT is the amount of current used to power

additional external circuitry.

DRIVE

gHIGH

gLOW

 F



Where:

-IDRIVE is the current required to drive the

external MOSFETs

-QgHIGH is the total gate charge of the

high-side MOSFET

-QgLOW is the total gate charge of the

low-side MOSFET

-FSW is the switching frequency

Note 1: The PE1<DRVSTR> bit configures the

peak source/sink current of the HDRV

pin.

Note 1: Refer to Figure 1-1 for a graphical

representation

the

MOSFET

connections.

Note 1: The DEADCON register controls the

amount of dead time added to the HDRV

or LDRV signal. The dead time circuitry is

enabled by the LDLYBY and HDLYBY

bits in the PE1 register.

OPTION_REG Datasheet(PDF) 15 Page - Microchip Technology

OPTION_REG Datasheet(HTML) 15 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL