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OPTION_REG Datasheet(PDF) 155 Page - Microchip Technology |
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OPTION_REG Datasheet(HTML) 155 Page - Microchip Technology |
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155 / 222 page  FIGURE 27-8: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1) Receiving Address Receiving Data Received Data P A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SDA SCL BF CKP S P 12 3 4 5 6 7 8 9 1 2 3 4 56 78 9 12 3 4 5 6 7 8 Master sends Stop condition S Data is read from SSPBUF Cleared by software SSPIF is set on 9th falling edge of SCL, after ACK CKP set by software, SCL is released Slave software 9 ACKTIM cleared by hardware in 9th rising edge of SCL sets ACKDT to not ACK When DHEN=1: CKP is cleared by hardware on 8th falling edge of SCL Slave software clears ACKDT to ACK the received byte ACKTIM set by hardware on 8th falling edge of SCL When AHEN=1: CKP is cleared by hardware and SCL is stretched Address is read from SSBUF ACKTIM set by hardware on 8th falling edge of SCL ACK Master Releases SDAx to slave for ACK sequence No interrupt after not ACK from Slave ACK=1 ACK ACKDT ACKTIM SSPIF If AHEN = 1: SSPIF is set |
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