DSPIC33FJ32GP204TESLASHML datasheet(4/403 Pages) MICROCHIP

4 / 403 page

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04

DS70292D-page 4

Preliminary

 2009 Microchip Technology Inc.

System Management:

• Flexible clock options:

- External, crystal, resonator, internal RC

- Fully integrated Phase-Locked Loop (PLL)

- Extremely low jitter PLL

• Power-up Timer

• Oscillator Start-up Timer/Stabilizer

• Watchdog Timer with its own RC oscillator

• Fail-Safe Clock Monitor

• Reset by multiple sources

Power Management:

• On-chip 2.5V voltage regulator

• Switch between clock sources in real time

• Idle, Sleep, and Doze modes with fast wake-up

Analog-to-Digital Converters (ADCs):

• 10-bit, 1.1 Msps or 12-bit, 500 ksps conversion:

- Two and four simultaneous samples (10-bit ADC)

- Up to 13 input channels with auto-scanning

- Conversion start can be manual or

synchronized with one of four trigger sources

- Conversion possible in Sleep mode

- ±2 LSb max integral nonlinearity

- ±1 LSb max differential nonlinearity

Audio Digital-to-Analog Converter (DAC):

• 16-bit Dual Channel DAC module

• 100 ksps maximum sampling rate

• Second-Order Digital Delta-Sigma Modulator

Data Converter Interface (DCI) module:

• Codec interface

• Supports I2S and AC’97 protocols

• Up to 16-bit data words, up to 16 words per frame

• 4-word deep TX and RX buffers

Comparator Module:

• Two analog comparators with programmable

input/output configuration

CMOS Flash Technology:

• Low-power, high-speed Flash technology

• Fully static design

• 3.3V (±10%) operating voltage

• Industrial and Extended temperature

• Low power consumption

Communication Modules:

• 4-wire SPI (up to two modules):

- Framing supports I/O interface to simple

codecs

- Supports 8-bit and 16-bit data

- Supports all serial clock formats and

sampling modes

•I2C™:

- Full Multi-Master Slave mode support

- 7-bit and 10-bit addressing

- Bus collision detection and arbitration

- Integrated signal conditioning

- Slave address masking

• UART (up to two modules):

- Interrupt on address bit detect

- Interrupt on UART error

- Wake-up on Start bit from Sleep mode

- 4-character TX and RX FIFO buffers

- LIN bus support

-IrDA® encoding and decoding in hardware

- High-Speed Baud mode

- Hardware Flow Control with CTS and RTS

• Enhanced CAN (ECAN™ module) 2.0B active:

- Up to eight transmit and up to 32 receive buffers

- 16 receive filters and three masks

- Loopback, Listen Only and Listen All

- Messages modes for diagnostics and bus

monitoring

- Wake-up on CAN message

- Automatic processing of Remote

Transmission Requests

- FIFO mode using DMA

- DeviceNet™ addressing support

• Parallel Master Slave Port (PMP/EPSP):

- Supports 8-bit or 16-bit data

- Supports 16 address lines

• Programmable Cyclic Redundancy Check (CRC):

- Programmable bit length for the CRC

generator polynomial (up to 16-bit length)

- 8-deep, 16-bit or 16-deep, 8-bit FIFO for data

input

Packaging:

• 28-pin SDIP/SOIC/QFN-S

• 44-pin TQFP/QFN

Note:

See the device variant tables for exact

peripheral features per device.

DSPIC33FJ32GP204TE/ML Datasheet(PDF) 4 Page - Microchip Technology

DSPIC33FJ32GP204TE/ML Datasheet(HTML) 4 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL