DSPIC33FJ32GP204TESLASHML datasheet(85/403 Pages) MICROCHIP

85 / 403 page

 2009 Microchip Technology Inc.

Preliminary

DS70292D-page 85

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04

FIGURE 6-3:

BROWN-OUT SITUATIONS

6.3

External Reset (EXTR)

The external Reset is generated by driving the MCLR

pin low. The MCLR pin is a Schmitt trigger input with an

additional glitch filter. Reset pulses that are longer than

the minimum pulse-width will generate a Reset. Refer

to Section 30.0 “Electrical Characteristics” for

minimum pulse-width specifications. The External

Reset (MCLR) Pin (EXTR) bit in the Reset Control

(RCON) register is set to indicate the MCLR Reset.

6.3.0.1

EXTERNAL SUPERVISORY CIRCUIT

Many systems have external supervisory circuits that

generate reset signals to Reset multiple devices in the

system. This external Reset signal can be directly con-

nected to the MCLR pin to Reset the device when the

rest of system is Reset.

6.3.0.2

INTERNAL SUPERVISORY CIRCUIT

When using the internal power supervisory circuit to

Reset the device, the external reset pin (MCLR) should

be tied directly or resistively to VDD. In this case, the

MCLR pin will not be used to generate a Reset. The

external reset pin (MCLR) does not have an internal

pull-up and must not be left unconnected.

6.4

Software RESET Instruction (SWR)

Whenever the RESET instruction is executed, the

device will assert SYSRST, placing the device in a spe-

cial Reset state. This Reset state will not re-initialize the

clock. The clock source in effect prior to the RESET

instruction will remain. SYSRST is released at the next

instruction cycle, and the reset vector fetch will com-

mence.

The Software Reset (Instruction) Flag (SWR) bit in the

Reset Control (RCON<6>) register is set to indicate

the software Reset.

6.5

Watchdog Time-out Reset (WDTO)

Whenever a Watchdog time-out occurs, the device will

asynchronously assert SYSRST. The clock source will

remain unchanged. A WDT time-out during Sleep or

Idle mode will wake-up the processor, but will not reset

the processor.

The Watchdog Timer Time-out Flag (WDTO) bit in the

Reset Control (RCON<4>) register is set to indicate

the

Watchdog

Reset.

Refer

Section 27.4

“Watchdog Timer (WDT)” for more information on

Watchdog Reset.

6.6

Trap Conflict Reset

If a lower-priority hard trap occurs while a higher-prior-

ity trap is being processed, a hard trap conflict Reset

occurs. The hard traps include exceptions of priority

level 13 through level 15, inclusive. The address error

(level 13) and oscillator error (level 14) traps fall into

this category.

The Trap Reset Flag (TRAPR) bit in the Reset Control

(RCON<15>) register is set to indicate the Trap Conflict

Reset. Refer to Section 7.0 “Interrupt Controller” for

more information on trap conflict Resets.

VDD

SYSRST

VBOR

VDD

SYSRST

VBOR

VDD

SYSRST

VBOR

TBOR + TPWRT

VDD dips before PWRT expires

TBOR + TPWRT

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