DSPIC33FJ32GP204TESLASHML datasheet(84/403 Pages) MICROCHIP

84 / 403 page

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04

DS70292D-page 84

Preliminary

 2009 Microchip Technology Inc.

6.2

Power-on Reset (POR)

A Power-on Reset (POR) circuit ensures the device is

reset from power-on. The POR circuit is active until

VDD crosses the VPOR threshold and the delay TPOR

has elapsed. The delay TPOR ensures the internal

device bias circuits become stable.

The device supply voltage characteristics must meet

the

specified

starting

voltage

and

rise

rate

requirements

generate

the

POR.

Refer

Section 30.0 “Electrical Characteristics” for details.

The POR status (POR) bit in the Reset Control

(RCON<0>) register is set to indicate the Power-on

Reset.

6.2.1

Brown-out Reset (BOR) and

Power-up timer (PWRT)

The on-chip regulator has a Brown-out Reset (BOR)

circuit that resets the device when the VDD is too low

(VDD < VBOR) for proper device operation. The BOR cir-

cuit keeps the device in Reset until VDD crosses VBOR

threshold and the delay TBOR has elapsed. The delay

TBOR ensures the voltage regulator output becomes

stable.

The BOR status (BOR) bit in the Reset Control

(RCON<1>) register is set to indicate the Brown-out

Reset.

The device will not run at full speed after a BOR as the

VDD should rise to acceptable levels for full-speed

operation. The PWRT provides power-up time delay

(TPWRT) to ensure that the system power supplies have

stabilized at the appropriate levels for full-speed

operation before the SYSRST is released.

The power-up timer delay (TPWRT) is programmed by

the

Power-on

Reset

Timer

Value

Select

(FPWRT<2:0>)

bits

the

POR

Configuration

(FPOR<2:0>) register, which provides eight settings

(from 0 ms to 128 ms). Refer to Section 27.0 “Special

Features” for further details.

Figure 6-3 shows the typical brown-out scenarios. The

reset delay (TBOR + TPWRT) is initiated each time VDD

rises above the VBOR trip point

TABLE 6-2:

OSCILLATOR DELAY

Symbol

Parameter

Value

VPOR

POR threshold

1.8V nominal

TPOR

POR extension time

s maximum

VBOR

BOR threshold

2.5V nominal

TBOR

BOR extension time

100

s maximum

TPWRT

Programmable power-up time delay

0-128 ms nominal

TFSCM

Fail-Safe Clock Monitor Delay

900

s maximum

Note:

When the device exits the Reset condi-

tion

(begins

normal

operation),

the

device operating parameters (voltage,

frequency, temperature, etc.) must be

within their operating ranges, otherwise

the device may not function correctly.

The user application must ensure that

the delay between the time power is

first applied, and the time SYSRST

becomes inactive, is long enough to get

all

operating

parameters

within

specification.

DSPIC33FJ32GP204TE/ML Datasheet(PDF) 84 Page - Microchip Technology

DSPIC33FJ32GP204TE/ML Datasheet(HTML) 84 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL