AN880 datasheet(4/14 Pages) STMICROELECTRONICS

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The L6569A holds both MOSFETs OFF until the

Under Voltage Lock Out is reached. This is in-

tended for inverters using 2 decoupling capacitors

in half bridge as shown on figure 12. The inverter

is totally off, so that the voltage at the capacitors

center node is not unbalanced by the leakage

path during power on.

CONSIDERATIONS ON THE L6569 ENVIRON-

MENT

To illustrate the benefits of the L6569 in the CFL

applications, a demonstration board was devel-

oped to supply Sylvania 18W DULUX lamp (ref:

CF18DT/E). The following chapters summarize

the application considerations applied in this de-

sign. The schematic, lay out and components list

are shown in appendix A.

Symmetric half bridge operation

To supply a fluorescent lamp, the ballast has to

achieve 3 functions: pre heat, ignition, and normal

lamp operation. The serial resonance occurs be-

tween the choke and the capacitor in parallel with

the lamp. The choice of these components deter-

mines the lamp ignition voltage and the nominal

lamp current.

Since the inverter using the L6569 and MOSFETs

can operate at a higher frequency than conven-

tional solutions, the size of the passive compo-

nents will be reduced. Such inverter can operate

up to 150 kHz in ZVS mode, and the switching

losses of the power transistors only limits the fre-

quency. In new design this frequency should be

set between 50 and 100 kHz. For instance with

an 18W lamp, a frequency increase from 33 to 50

kHz will lead to a 40% reduction of the choke

size.

To operate in Zero Voltage Switching (ZVS), the

switching frequency is higher than the resonant

frequency. All operation phases of the ballast are

secure in this mode. When the bootstrap transis-

tor is conducting, no pulse current will flow from

pin BOOT to pin VS, as it might happen in Zero

Current Switching. The bootstrap transistor re-

mains in its Safe Operating Area, and its dissipa-

tion is negligible.

The MOSFET drive

The ZVS drive technique requires only a fast turn

off capability as shown on figure 2, and the tran-

sistor buffers are designed with a stronger sink

current. The two MOSFET buffers of the L6569

can sink a 400 mA peak current on capacitive

load. Typically these buffers can drive any MOS-

FETs in TO220 package.

Figure 7 shows an example with the STP8NA50

that has an 0.85

Ω resistance RDS-ON.

The built-in dead time circuit acts when a MOS-

FET turns off, delaying the turn on of the opposite

transistor for 1.25

µs. The voltage VOUT between

the 2 MOSFETs must switch within the minimum

dead time (0.85

µs), as shown on figure 8, to

avoid bridge cross conductions and transistors

overheat.

The MOSFET voltage selection

Since the ballast is connected to the ac mains, it

must handle any spurious voltage spikes. When

the front end RFI filter and the clamping device,

such as a varistor, absorbes totally the spike en-

ergy, MOSFETs can have the same 600V mini-

mum breakdown voltage BVDSS as the L6569.

Otherwise when the upper MOSFET is on, the re-

sidual default may be applied to the L6569. Al-

though the pin OUT breakdown voltage is higher

than 600V, it has a poor avalanche robustness.

Therefore the lower MOSFET protects the driver

by having a lower BVDSS. A MOSFET with a mini-

mum BVDSS up to 500V will achieve safely this

task.

50 ns/dv ; 1 A/dv ; 5 V/dv ; 50V/dv

VGS

GND

TGD

Figure 7: Current and voltage of the STP8NA50

MOSFET at turn off with the L6569.

TGD = 245 ns ,Tc = 95 ns, E = 93

µJ

@ Tj = 50°C, RG = 22

Ω.

200 ns/dv ; 50 V/dv ; 0.1 A/dv

LVG

VDS

TGD

GND

Figure 8: STD3NA50 MOSFET turn off when

driven by the L6569. TC + TGD < TD

AN880 APPLICATION NOTE

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