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T89C5115-RATIM Datasheet(PDF) 83 Page - ATMEL Corporation |
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T89C5115-RATIM Datasheet(HTML) 83 Page - ATMEL Corporation |
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83 / 105 page  83 T89C5115 4128A–8051–04/02 Table 57. ADCLK Register ADCLK (S:F2h) ADC Clock Prescaler Reset Value = XXX0 0000b Table 58. ADDH Register ADDH (S:F5h Read Only) ADC Data High byte register Reset Value = 00h Table 59. ADDL Register ADDL (S:F4h Read Only) ADC Data Low byte register Reset Value = 00h 76 54 32 1 0 - - - PRS 4 PRS 3 PRS 2 PRS 1 PRS 0 Bit Number Bit Mnemonic Description 7-5 - Reserved The value read from these bits are indeterminate. Do not set these bits. 4-0 PRS4:0 Clock Prescaler fADC = fcpu clock/ (4 (or 2 in X2 mode)* (PRS +1)) 76 54 32 1 0 ADAT 9 ADAT 8 ADAT 7 ADAT 6 ADAT 5 ADAT 4 ADAT 3 ADAT 2 Bit Number Bit Mnemonic Description 7-0 ADAT9:2 ADC result bits 9-2 76 54 32 1 0 - - - - - - ADAT 1 ADAT 0 Bit Number Bit Mnemonic Description 7-2 - Reserved The value read from these bits are indeterminate. Do not set these bits. 1-0 ADAT1:0 ADC result bits 1-0 |
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