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T89C5115-RATIM Datasheet(PDF) 87 Page - ATMEL Corporation |
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T89C5115-RATIM Datasheet(HTML) 87 Page - ATMEL Corporation |
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87 / 105 page  87 T89C5115 4128A–8051–04/02 Table 63. IEN1 Register IEN1 (S:E8h) Interrupt Enable Register Reset Value = xxxx xx0xb bit addressable 76 54 32 1 0 -- --- - EADC - Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3- Reserved The value read from this bit is indeterminate. Do not set this bit. 2- Reserved The value read from this bit is indeterminate. Do not set this bit. 1 EADC ADC Interrupt Enable bit Clear to disable the ADC interrupt. Set to enable the ADC interrupt. 0- Reserved The value read from this bit is indeterminate. Do not set this bit. |
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