 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
TNETV1647GSTZWT Datasheet(PDF) 121 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
TNETV1647GSTZWT Datasheet(HTML) 121 Page - Texas Instruments |
|
|
121 / 236 page  TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.7.3 ARM/DSP Communications Interrupts The INTGEN register is used for generating interrupts between the ARM and DSP. The INTGEN register format is shown in Figure 6-18. Table 6-24 describes the register bit fields. The ARM may generate an interrupt to the DSP by setting one of the four INTDSP[3:0] bits or the INTNMI bit. The interrupt bit automatically self clears and the corresponding DSP[3:0]STAT or NMISTAT bit is automatically set to indicate that the interrupt was generated. After servicing the interrupt, the DSP clears the status bit by writing ‘0’. The ARM may poll the status bit to determine when the DSP has completed servicing the interrupt. The DSP may generate an interrupt to the ARM in the same manner using the INTARM[1:0] bits and monitor ARM interrupt servicing via the ARM[1:0]STAT bits. Figure 6-18. INTGEN Register 31 30 29 28 27 24 23 22 21 20 19 17 16 ARM1 ARM0 DSP3 DSP2 DSP1 DSP0 NMI RESERVED RESERVED RESERVED STAT STAT STAT STAT STAT STAT STAT R-00 R/W-0 R/W-0 R-0000 R/W-0 R/W-0 R/W-0 R/W-0 R-000 R/W-0 15 14 13 12 11 8 7 6 5 4 3 1 0 INT INT INT INT INT INT INT RESERVED RESERVED RESERVED ARM1 ARM0 DSP3 DSP2 DSP1 DSP0 NM I R-00 R/W-0 R/W-0 R-0000 R/W-0 R/W-0 R/W-0 R/W-0 R-000 R/W-0 LEGEND: R = Read, W = Write, n = value at reset Table 6-24. INTGEN Register Bit Field Descriptions Bit Field Value Description 31 - 30 RESERVED Reserved 29 ARM1STAT DSP to ARM Int1 Status/Clear(1) 28 ARM0STAT DSP to ARM Int0 Status/Clear(1) 27 - 24 RESERVED Reserved 23 DSP3STAT ARM to DSP Int3 Status/Clear(1) 22 DSP2STAT ARM to DSP Int2 Status/Clear(1) 21 DSP1STAT ARM to DSP Int1 Status/Clear(1) 20 DSP0STAT ARM to DSP Int0 Status/Clear(1) 19 - 17 RESERVED Reserved 16 NMISTAT DSP NMI Status/Clear(1) 15 - 14 RESERVED Reserved 13 INTARM1 DSP to ARM Int1 Set(2) 12 INTARM0 DSP to ARM Int0 Set(2) 11 - 8 RESERVED Reserved 7 INTDSP3 ARM to DSP Int3 Set(2) 6 INTDSP2 ARM to DSP Int2 Set(2) 5 INTDSP1 ARM to DSP Int1 Set(2) 4 INTDSP0 ARM to DSP Int0 Set(2) 3 - 1 RESERVED Reserved 0 INTNMI DSP NMI Set(2) (1) Write '0' to clear. Writing '1' has no effect. (2) Write '1' to generate the interrupt. The register bit automatically clears to a value of '0'. Writing a '0' has no effect. Copyright © 2006–2010, Texas Instruments Incorporated Peripheral and Electrical Specifications 121 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
British ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
