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56F8167 Datasheet(PDF) 150 Page - Freescale Semiconductor, Inc |
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56F8167 Datasheet(HTML) 150 Page - Freescale Semiconductor, Inc |
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150 / 184 page  56F8367 Technical Data, Rev. 7.0 150 Freescale Semiconductor Preliminary Table 10-16 External Memory Interface Timing Characteristic Symbol Wait States Configuration DM Wait States Controls Unit Address Valid to WR Asserted tAWR WWS=0 -2.076 0.50 WWSS ns WWS>0 -1.795 0.75 + DCAOE WR Width Asserted to WR Deasserted tWR WWS=0 -0.094 0.25 + DCAOE WWS ns WWS>0 -0.012 0 Data Out Valid to WR Asserted tDWR WWS=0 -9.321 0.25 + DCAEO WWSS ns WWS=0 -1.160 0.00 WWS>0 -8.631 0.50 WWS>0 -0.879 0.25 + DCAOE Valid Data Out Hold Time after WR Deasserted tDOH -2.086 0.25 + DCAEO WWSH ns Valid Data Out Set-Up Time to WR Deasserted tDOS -0.563 0.25 + DCAOE WWS,WWSS ns -8.315 0.50 Valid Address after WR Deasserted tWAC -3.432 0.25 + DCAEO WWSH ns RD Deasserted to Address Invalid tRDA -1.780 0.00 RWSH ns Address Valid to RD Deasserted tARDD -2.120 1.00 RWSS,RWS ns Valid Input Data Hold after RD Deasserted tDRD 0.00 N/A1 1. N/A since device captures data before it deasserts RD — ns RD Assertion Width tRD 0.279 1.00 RWS ns Address Valid to Input Data Valid tAD -15.723 1.00 RWSS,RWS ns -20.642 1.25 + DCAOE Address Valid to RD Asserted tARDA -2.603 0.00 RWSS ns RD Asserted to Input Data Valid tRDD -13.120 1.00 RWSS,RWS ns -18.039 1.25 + DCAOE WR Deasserted to RD Asserted tWRRD -2.135 0.25 + DCAEO WWSH,RWSS ns RD Deasserted to RD Asserted tRDRD -0.4832 2. If RWSS = RWSH = 0, and the chip select does not change, then RD does not deassert during back-to-back reads. 0.00 RWSS,RWSH MDAR3, 4 3. Substitute BMDAR for MDAR if there is no chip select 4. MDAR is active in this calculation only when the chip select changes. ns WR Deasserted to WR Asserted tWRWR WWS=0 -1.608 0.75 + DCAEO WWSS, WWSH ns WWS>0 -0.918 1.00 RD Deasserted to WR Asserted tRDWR WWS=0 -0.096 0.50 RWSH, WWSS, MDAR3 ns WWS>0 0.084 0.75 + DCAOE |
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