STM32F479 datasheet(48/91 Pages) STMICROELECTRONICS

48 / 91 page

Creating a graphical application with LTDC

AN4861

48/91

DocID029237 Rev 2

Figure 28. Placing the two buffers in independent SDRAM banks

For instance, when the SDRAM bank size is equal to 4 MByte, the following line code can

be used:

/* Framebuffer addresses within external SDRAM */

/* Frontbuffer in bank 1 of SDRAM memory */

uint32_t FrontBuffer

= LCD_FB_START_ADRESS;

/* Backbuffer in the bank 2 of SDRAM memory */

uint32_t BackBuffer

= LCD_FB_START_ADRESS + 1024 * 1024 * 4;

SDRAM RBURST

Another interesting feature allowing to optimize the reading performances from the SDRAM

is the use of RBURST.

The SDRAM controller adds a cacheable read FIFO with a depth of 6 32-bit lines. The read

FIFO is used when the read burst is enabled and allows to anticipate the next read

accesses during CAS latencies.

4.5.4

Framebuffer content update during BLANKING period

A way to optimize graphic performance (especially when the performance bottleneck is the

framebuffer memory bandwidth), is to update the framebuffer content during the blanking

period. Since in this period the LTDC is not fetching any pixel data from the framebuffer, the

bus bandwidth is relaxed and it allows the update of the framebuffer.

4.6

Special recommendations for Cortex®-M7 (STM32F7 Series)

This section illustrates some recommendations for the STM32F7 Series embedding the

Cortex®-M7 CPU. These recommendations are specific to the Cortex®-M7 since it has the

following particularities compared to the Cortex®-M4 CPU:

•

The Cortex®-M7 does some speculative read accesses to normal memory regions.

These speculative read accesses could cause high latency or system errors when

performed on external memories like SDRAM or Quad-SPI. This impacts AHB masters

(such as LTDC) accessing the FMC or Quad-SPI and particularly decreases graphical

STM32F479 Datasheet(PDF) 48 Page - STMicroelectronics