STM32F479 datasheet(43/91 Pages) STMICROELECTRONICS

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AN4861

Creating a graphical application with LTDC

As shown in the example described in Figure 24, the SRAM2 and SRAM3 are dedicated to

graphics for the framebuffer while the SRAM1 is used by the CPU.

Figure 24. Example of taking advantage from memory slaves split

on the STM32F4x9 line MCUs

4.5.2

Optimizing the LTDC framebuffer fetching from external memories

(SDRAM or SRAM)

Another consideration related to the SDRAM/SRAM, is the placement of the framebuffer

and the line length data size. Since the AHB Bus matrix prohibits a memory burst access

that crosses the one Kilobyte boundary and as the LTDC performs burst read of 64 bytes,

placing the content of the framebuffer in an address at the edge of one kilobyte splits the

burst read into single accesses, which can heavily affect the graphical performances.

The same problem can occur when the data size of one line of pixels is not a multiple of

64 bytes. Under these conditions and after a number of accesses, the LTDC read burst

crosses the Kilobyte boundary which splits the burst read into single accesses.

As a consequence, when the LTDC is not generating a burst, each access is interrupted by

a CPU or another master access (Chrom-Art Accelerator®, Ethernet, or other). This

interruptions highly reduce the LTDC bandwidth on a high latency memory like the external

SDRAM, which leads to an underrun.

To solve the issue described above, the user may choose a color depth that does not lead to

the described issue or use one of the two following methods:

•

Reduce the layer window and the framebuffer line widths.

•

Add a number of dummy bytes at the end of every line of pixels to match the closest

frame line width multiple of 64 bytes.

STM32F479 Datasheet(PDF) 43 Page - STMicroelectronics