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XRT83SL34IV Datasheet(PDF) 15 Page - Exar Corporation |
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XRT83SL34IV Datasheet(HTML) 15 Page - Exar Corporation |
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15 / 80 page  XRT83SL34 QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR PRELIMINARY REV. P1.0.8 12 CLOCK SYNTHESIZER SIGNAL NAME PIN #TYPE DESCRIPTION MCLKE1 32 I E1 Master Clock Input A 2.048MHz clock for with an accuracy of better than ±50ppm and a duty cycle of 40% to 60% can be provided at this pin. In systems that have only one master clock source available (E1 or T1), that clock should be connected to both MCLKE1 and MCLKT1 inputs for proper operation. NOTES: 1. All channels of the XRT83SL34 must be operated at the same clock rate, either T1, E1 or J1. 2. Internally pulled “Low” with a 50k Ω resistor. CLKSEL0 CLKSEL1 CLKSEL2 37 38 39 I Clock Select inputs for Master Clock Synthesizer - Hardware mode CLKSEL[2:0] are input signals to a programmable frequency synthesizer that can be used to generate a master clock from an accurate external clock source according to the following table. The MCLKRATE control signal is generated from the state of EQC[4:0] inputs. See Table 4 for description of Transmit Equalizer Control bits. Host Mode: The state of these pins are ignored and the master frequency PLL is controlled by the corresponding interface bits. See Table 35, register address 1000001. NOTE: These pins are internally pulled "Low" with a 50k Ω resistor. 2048 2048 2048 1544 MCLKE1 (kHz) 8 16 16 56 8 56 64 64 128 256 256 128 2048 2048 1544 1544 MCLKT1 (kHz) 1544 X X X 1544 X X X X X X X 2048 1544 2048 CLKOUT (KHz) 1544 2048 1544 2048 1544 2048 1544 2048 1544 2048 1544 2048 1544 0 0 1 1 CLKSEL0 0 1 1 0 0 0 1 1 0 1 1 0 0 0 0 0 CLKSEL1 1 1 1 0 1 0 0 0 1 1 1 1 0 0 0 0 CLKSEL2 0 0 0 1 0 1 1 1 1 1 1 1 0 1 0 0 0 0 1544 2048 X X 2048 1544 0 1 0 1 MCLKRATE 1 0 1 0 0 1 0 1 1 0 1 0 0 1 |
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