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XRT83SL34IV Datasheet(PDF) 56 Page - Exar Corporation |
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XRT83SL34IV Datasheet(HTML) 56 Page - Exar Corporation |
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56 / 80 page  XRT83SL34 QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.0.8 PRELIMINARY 53 TABLE 24: MICROPROCESSOR REGISTER #5, BIT DESCRIPTION REGISTER ADDRESS 0000101 0010101 0100101 0110101 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 FUNCTION REGISTER TYPE RESET VALUE BIT #NAME D7 Reserved RO 0 D6 DMO_n Driver Monitor Output: This bit is set to a “1” to indicate transmit driver failure is detected. The value of this bit is based on the current status of DMO for the corresponding channel. If the DMOIE bit is enabled, any transition on this bit will gener- ate an Interrupt. RO 0 D5 FLS_n FiFO Limit Status: This bit is set to a “1” to indicate that the jit- ter attenuator read/write FIFO pointers are within +/- 3 bits. If the FLSIE bit is enabled, any transition on this bit will generate an Interrupt. RO 0 D4 LCV_n Line Code Violation: This bit is set to a “1” to indicate that the receiver of channel n is currently detecting a Line Code Viola- tion or an excessive number of zeros in the B8ZS or HDB3 modes. If the LCVIE bit is enabled, any transition on this bit will generate an Interrupt. RO 0 |
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