XRT83SL34IV datasheet(44/80 Pages) EXAR

44 / 80 page

XRT83SL34

QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.0.8

PRELIMINARY

MICROPROCESSOR PARALLEL INTERFACE

XRT83SL34 is equipped with a microprocessor interface for easy device configuration. The parallel port of the

XRT83SL34 is compatible with both Intel and Motorola address and data buses. The XRT83SL34 has an 8-bit

address A[7:0] input and 8-bit bi-directional data bus D[7:0]. The signals required for a generic microprocessor

to access the internal registers are described in Table 16.

TABLE 16: MICROPROCESSOR INTERFACE SIGNAL DESCRIPTION

D[7:0]

Data Input (Output): 8 bits bi-directional Read/Write data bus for register access.

A[7:0]

Address Input: 8 bit address to select internal register location.

µPTS1

µPTS2

Microprocessor Type Select:

µPCLK

Microprocessor Clock Input: Input clock for synchronous microprocessor operation. Maximum

clock speed is 54MHz. This pin is internally pulled “Low” for asynchronous microprocessor operation

when no clock is present.

ALE_AS

Address Latch Input (Address Strobe):

-Intel bus timing, the address inputs are latched into the internal register on the falling edge of ALE.

-Motorola bus timing, the address inputs are latched into the internal register on the falling edge of

AS.

Chip Select Input: This signal must be “Low” in order to access the parallel port.

RD_DS

Read Input (Data Strobe):

-Intel bus timing, a “Low” pulse on RD selects a read operation when CS pin is “Low”.

-Motorola bus timing, a “Low” pulse on DS indicates a read or write operation when CS pin is “Low”.

WR_R/W

Write Input (Read/Write):

-Intel bus timing, a “Low” pulse on WR selects a write operation when CS pin is “Low”.

-Motorola bus timing, a “High” pulse on R/W selects a read operation and a “Low” pulse on R/W

selects a write operation when CS pin is “Low”.

RDY_DTACK

Ready Output (Data Transfer Acknowledge Output):

-Intel bus timing, RDY is asserted “High” to indicate the XRT83SL34 has completed a read or write

operation.

-Motorola bus timing, DTACK is asserted “Low” to indicate the XRT83SL34 has completed a read or

write operation.

INT

Interrupt Output: This pin is asserted “Low” to indicate an interrupt caused by an alarm condition in

the device status registers. The activation of this pin can be blocked by setting the GIE bit to “0” in the

Command Control register.

µPTS2

µPTS1

µP Type

68H C 11, 8051, 80C 188 (a syn c.)

M o to ro la 6 8 K (a syn c.)

In te l x8 6 (syn c.)

In te l i960, M o to ro la 860 (syn c.)

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