XRT83SL34IV datasheet(48/80 Pages) EXAR

48 / 80 page

XRT83SL34

QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.0.8

PRELIMINARY

MICROPROCESSOR REGISTER DESCRIPTIONS

TABLE 19: MICROPROCESSOR REGISTER #0, BIT DESCRIPTION

0000000

0010000

0100000

0110000

CHANNEL_n

CHANNEL_0

CHANNEL_1

CHANNEL_2

CHANNEL_3

FUNCTION

TYPE

RESET

VALUE

BIT #NAME

Reserved

R/W

Reserved

R/W

RXON_n

Receiver ON: Writing a “1” into this bit location turns on the

Receive Section of channel n. Writing a “0” shuts off the

Receiver Section of channel n.

NOTES:

This bit provides independent turn-off or turn-on

control of each receiver channel.

In Hardware mode all receiver channels are always

on.

R/W

EQC4_n

Equalizer Control bit 4: This bit together with EQC[3:0] are

used for controlling transmit pulse shaping, transmit line build-

out (LBO) and receive monitoring for either T1 or E1 Modes of

operation.

See

Table 5 for description of Equalizer Control bits.

R/W

EQC3_n

Equalizer Control bit 3: See bit D4 description for function of

this bit

R/W

EQC2_n

Equalizer Control bit 2: See bit D4 description for function of

this bit

R/W

EQC1_n

Equalizer Control bit 1: See bit D4 description for function of

this bit

R/W

EQC0_n

Equalizer Control bit 0: See bit D4 description for function of

this bit

R/W

XRT83SL34IV Datasheet(PDF) 48 Page - Exar Corporation

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