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XRT83SL34IV Datasheet(PDF) 68 Page - Exar Corporation |
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XRT83SL34IV Datasheet(HTML) 68 Page - Exar Corporation |
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68 / 80 page  XRT83SL34 QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.0.8 PRELIMINARY 65 D3 SL_1 Slicer Level Control bit 1: This bit and bit D2 control the slic- ing level for the slicer per the following table. R/W 0 D2 SL_0 Slicer Level Control bit 0: See description bit D3. R/W 0 D1 EQG_1 Equalizer Gain Control bit 1: This bit together with bit D0 control the gain of the equalizer as shown in the table below. R/W 0 D0 EQG_0 Equalizer Gain Control bit 0: See description of bit D1 R/W 0 TABLE 37: MICROPROCESSOR REGISTER #66, BIT DESCRIPTION SL_1 SL_0 0 0 0 1 1 0 1 1 Slicer Mode Normal Decrease by 5% from Normal Increase by 5% from Normal Normal EQG_1 EQG_0 0 0 0 1 1 0 1 1 Equalizer Gain Normal Reduce Gain by 1 dB Reduce Gain by 3 dB Normal |
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