ADRF6755ACPZ-R7 datasheet(25/48 Pages) AD

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Data Sheet

ADRF6755

Rev. B | Page 25 of 48

frequencies must be performed to ensure optimum carrier feed-

through across the full frequency range.

Sideband Suppression Nulling

Sideband suppression results from relative gain and relative phase

offsets between the I channel and Q channel and can be optimized

through adjustments to those two parameters. Adjusting only

one parameter improves the sideband suppression only to a

point. For optimum sideband suppression, an iterative adjustment

between phase and amplitude is required.

ATTENUATOR

The digital attenuator consists of six attenuation blocks: 1 dB,

2 dB, 4 dB, 8 dB, and two 16 dB blocks; each is separately

controlled. Each attenuation block consists of field effect transistor

(FET) switches and resistors that form either a pi-shaped or a

T-shaped attenuator. By controlling the states of the FET switches

through the control lines, each attenuation block can be set to

the pass state (0 dB) or the attenuation state (1 dB to 47 dB).

The various combinations of the six blocks provide the

attenuation states from 0 dB to 47 dB in 1 dB increments.

VOLTAGE REGULATOR

The voltage regulator is powered from a 5 V supply that is

provided by VCC1 (Pin 11) and produces a 3.3 V nominal

regulated output voltage, REGOUT, on Pin 12. This pin must

be connected (external to the IC) to the VREG1 through VREG6

package pins.

Decouple the regulator output (REGOUT) with a parallel

combination of 10 pF and 220 µF capacitors. The 220 µF

capacitor, which is recommended for best performance,

decouples broadband noise, leading to better phase noise. Each

VREGx pin should have the following decoupling capacitors:

100 nF multilayer ceramic with an additional 10 pF in parallel,

both placed as close as possible to the device under test (DUT)

power supply pins. X7R or X5R capacitors are recommended.

See the Evaluation Board section for more information.

I2C INTERFACE

The ADRF6755 supports a 2-wire, I2C-compatible serial bus

that drives multiple peripherals. The serial data (SDA) and serial

clock (SCL) inputs carry information between any devices that

are connected to the bus. Each slave device is recognized by a

unique address. The ADRF6755 has two possible 7-bit slave

addresses for both read and write operations. The MSB of the

7-bit slave address is set to 1. Bit A5 of the slave address is set by

the CS pin (Pin 27). Bits[4:0] of the slave address are set to all

0s. The slave address consists of the seven MSBs of an 8-bit

word. The LSB of the word sets either a read or a write operation

(see Figure 63). Logic 1 corresponds to a read operation, whereas

Logic 0 corresponds to a write operation.

To control the device on the bus, the following protocol must

be followed. The master initiates a data transfer by establishing

a start condition, defined by a high-to-low transition on SDA

while SCL remains high. This indicates that an address/data

stream follows. All peripherals respond to the start condition

and shift the next eight bits (the 7-bit address and the R/W bit).

The bits are transferred from MSB to LSB. The peripheral that

recognizes the transmitted address responds by pulling the data

line low during the ninth clock pulse. This is known as an

acknowledge bit. All other devices then withdraw from the bus

and maintain an idle condition. During the idle condition, the

device monitors the SDA and SCL lines waiting for the start

condition and the correct transmitted address. The R/W bit

determines the direction of the data. Logic 0 on the LSB of the

first byte indicates that the master writes information to the

peripheral. Logic 1 on the LSB of the first byte indicates that the

master reads information from the peripheral.

The ADRF6755 acts as a standard slave device on the bus. The data

on the SDA pin (Pin 29) is eight bits long, supporting the 7-bit

addresses plus the R/W bit. The ADRF6755 has 34 subaddresses

to enable the user-accessible internal registers. Therefore, it

interprets the first byte as the device address and the second

byte as the starting subaddress. Auto-increment mode is supported,

which allows data to be read from or written to the starting sub-

address and each subsequent address without manually addressing

the subsequent subaddress. A data transfer is always terminated

by a stop condition. The user can also access any unique subaddress

Stop and start conditions can be detected at any stage of the data

transfer. If these conditions are asserted out of sequence with

normal read and write operations, they cause an immediate jump

to the idle condition. If an invalid subaddress is issued by the

user, the ADRF6755 does not issue an acknowledge and returns to

the idle condition. In a no acknowledge condition, the SDA line is

not pulled low on the ninth pulse. See Figure 64 and Figure 65

for sample write and read data transfers, Figure 66 for the timing

protocol, and Figure 2 for a more detailed timing diagram.

Figure 63. Slave Address Configuration

MSB = 1

SET BY

PIN 27

(CS)

0 = WR

1 = RD

SLAVE ADDRESS[6:0]

R/W

CTRL

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