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ADRF6755ACPZ-R7 Datasheet(PDF) 9 Page - Analog Devices

Part # ADRF6755ACPZ-R7
Description  100 MHz to 2400 MHz I/Q Modulator with Integrated Fractional-N PLL and VCO
PDF  48 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADRF6755ACPZ-R7 Datasheet(HTML) 9 Page - Analog Devices

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Data Sheet
ADRF6755
Rev. B | Page 9 of 48
SPI Interface Timing
Table 3.
Parameter1
Symbol
Limit
Unit
CLK Frequency
fCLK
20
MHz max
CLK Pulse Width High
t1
15
ns min
CLK Pulse Width Low
t2
15
ns min
Start Condition Hold Time
t3
5
ns min
Data Setup Time
t4
10
ns min
Data Hold Time
t5
5
ns min
Stop Condition Setup Time
t6
5
ns min
SDO Access Time
t7
15
ns min
CS to SDO High Impedance
t8
25
ns max
1 See Figure 3.
Figure 3. SPI Port Timing Diagram
t1
t3
CS
CLK
SDI
SDO
t6
t8
t7
t2
t5
t4



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