ADRF6755ACPZ-R7 datasheet(37/48 Pages) AD

37 / 48 page

Data Sheet

ADRF6755

Rev. B | Page 37 of 48

EVALUATION BOARD

GENERAL DESCRIPTION

The EVAL-ADRF6755SDZ evaluation board is designed to allow

the user to evaluate the performance of the ADRF6755. It contains

the following:

•

I/Q modulator with integrated fractional-N PLL and VCO

•

Connector to interface to a standard USB interface board

(SPD-S) that must be ordered with the EVAL-ADRF6755SDZ

board.

•

DC biasing and filter circuitry for the baseband inputs

•

Low-pass loop filter circuitry

•

An 80 MHz reference clock

•

Circuitry to monitor the LOMON outputs

•

SMA connectors for power supplies and the RF output

The evaluation board is supplied with the associated driver

software to allow easy programming of the ADRF6755.

HARDWARE DESCRIPTION

For more information, refer to the circuit diagram in Figure 70.

Power Supplies

An external 5 V supply, DUT +5 V (J14), drives both an on-chip

3.3 V regulator and the quadrature modulator.

The regulator feeds the VREG1 through VREG6 pins on the

chip with 3.3 V. These pins power the PLL circuitry.

The external reference clock generator should be driven by a

3.3 V supply. This supply should be connected via an SMA

connector, OSC +V (J15).

Recommended Decoupling for Supplies

The external DUT +5 V supply is decoupled initially by a 10 µF

capacitor and then further by a parallel combination of 100 nF

and 10 pF capacitors that are placed as close to the DUT as

possible for good local decoupling. The regulator output should

be decoupled by a parallel combination of 10 pF and 220 µF

capacitors. The 220 µF capacitor decouples broadband noise,

which leads to better phase noise and is recommended for best

performance. Case Size C 220 µF capacitors are used to minimize

area. Place a parallel combination of 100 nF and 10 pF capacitors

on each VREGx pin, as close to the pins as possible. The impedance

of these capacitors should be low and constant across a broad

frequency range. Surface-mount multilayered ceramic chip

(MLCC) Class II capacitors provide very low ESL and ESR, which

assist in decoupling supply noise effectively. They also provide

good temperature stability and good aging characteristics.

Capacitance also changes vs. applied bias voltage. Larger case

sizes have less capacitance change vs. applied bias voltage and

have lower ESR but higher ESL. The 0603 size capacitors provide a

good compromise. X5R and X7R capacitors are examples of

these types of capacitors and are recommended for decoupling.

SPI Interface

The SPI interface is provided by an additional SPD-S board. This

must be ordered with the ADRF6755 evaluation board. The system

demonstration platform (SDP) is a hardware and software platform

that provides a means to communicate from the PC to Analog

Devices products and systems that require digital control and/or

readback (see Figure 71).

The SDP-S controller board connects to the PC via USB 2.0 and

to the ADRF6755 evaluation board via a small footprint, 120-pin

connector. The SDP-S (serial only interface) is a low cost, small

form factor, SDP controller board.

Baseband Inputs

The pair of I and Q baseband inputs are served by SMA inputs

(J2 to J5) so that they can be driven directly from an external

generator or a DAC board, both of which can also provide the

dc bias required. There is also an option to filter the baseband

inputs, although filtering may not be required, depending on

the quality of the baseband source.

Loop Filter

A fourth-order loop filter is provided at the output of the charge

pump and is required to adequately filter noise from the Σ-Δ

modulator used in the N-divider. With the charge pump current

set to a value of 5 mA and using the on-chip VCO, the loop

bandwidth is approximately 100 kHz, and the phase margin is

55°. C0G capacitors are recommended for use in the loop filter

because they have low dielectric absorption, which is required

for fast and accurate settling time. The use of non-C0G capacitors

may result in a long tail being introduced into the settling time

transient.

Reference Input

The reference input can be supplied by an 80 MHz Jauch clock

generator or by an external clock through the use of Connector

REFIN (J7). The frequency range of the PFD input is from 10 MHz

to 40 MHz; if the 80 MHz clock generator is used, the on-chip 5-bit

reference frequency divider or the divide-by-2 divider should be

used to set the PFD frequency to 40 MHz to optimize phase noise

performance.

LOMON Outputs

These pins are differential LO monitor outputs that provide a

replica of the internal LO frequency at 1× LO. The single-ended

power in a 50 Ω load can be programmed to −24 dBm, −18 dBm,

−12 dBm, or −6 dBm. These open-collector outputs must be

terminated to 3.3 V. Because both outputs must be terminated

to 50 Ω, options are provided to terminate to 3.3 V using on-

board 50 Ω resistors or by series inductors (or a ferrite bead),

in which case the 50 Ω termination is provided by the measuring

instrument. If not used, these outputs should be tied to REGOUT.

ADRF6755ACPZ-R7 Datasheet(PDF) 37 Page - Analog Devices

ADRF6755ACPZ-R7 Datasheet(HTML) 37 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Datasheet Download

Link URL