ADRF6755ACPZ-R7 datasheet(18/48 Pages) AD

18 / 48 page

ADRF6755

Data Sheet

Rev. B | Page 18 of 48

Figure 35. PLL Frequency Settling Time at Worst-Case LO Frequency

with Lock Detect Shown

Figure 36. Attenuator Gain vs. LO Frequency by Gain Code, All Attenuator

Code Steps

Figure 37. Attenuator Relative Step Accuracy over all Attenuation Steps

vs. LO Frequency, Nominal Conditions

Figure 38. Attenuator Relative Step Accuracy Distribution at Nominal

and Worst-Case Conditions, LO > 300 MHz, All Attenuation Steps

Figure 39. Attenuator Relative Step Accuracy Across Full Output

Frequency Range Distribution at Nominal and Worst-Case Conditions,

LO > 300 MHz, All Attenuation Steps

Figure 40. Attenuator Absolute Step Accuracy over all Attenuation Steps

vs. LO Frequency, Nominal Conditions

0.1

100

10k

100k

10M

100M

–50 –30 –10 10 30 50 70 90 110 130 150 170 190 210 230 250

TIME (µs)

START OF

ACQUISITION

TO 100Hz

NUMBER OF PFD

CYCLES TO DECLARE

LDET = 4096

LDET

–50

–45

–40

–35

–30

–25

–20

–15

–10

–5

100 300 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500

LO FREQUENCY (MHz)

–1.5

–1.0

–0.5

0.5

1.0

100 300 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500

LO FREQUENCY (MHz)

–1.0

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

1.0

ATTENUATOR RELATIVE STEP ACCURACY (dB)

NOMINAL

WORST CASE

–3.25

–2.75

–2.25

–1.75

–1.25

–0.75

–0.25

0.25

0.75

1.25

1.75

2.25

2.75

3.25

ATTENUATOR RELATIVE STEP ACCURACY ACROSS

FULL OUTPUT FREQUENCY RANGE (dB)

NOMINAL

WORST CASE

–10

–8

–6

–4

–2

100 300 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500

LO FREQUENCY (MHz)

ADRF6755ACPZ-R7 Datasheet(PDF) 18 Page - Analog Devices

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