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L9177ATR Datasheet(PDF) 24 Page - STMicroelectronics |
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L9177ATR Datasheet(HTML) 24 Page - STMicroelectronics |
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24 / 55 page ![]() Symbol Parameter Test conditions Min Typ Max Unit tCSSO Access time See (1) - - 500 ns tSOdis Output data (SO) disable time No Capacitor on SO, See (2) - - 500 ns tlead Channels select (CS) lead time See (1) 500 - - ns tSCKFSO Output valid time See (1), @ fCLK= 5.4 MHz 60 - - ns tSOCS Output data (SO) disable time No capacitor on SO, see (1) - 500 ns tSIsetup Input data (SI) set-up time @ fCLK= 5.4 MHz 20 - - ns tSIhold Input data (SI) hold time @ fCLK= 5.4 MHz 20 - - ns tSCK CLK period - 185 - - ns tCSSCK Clock inactive time after frame - 600 - - ns tCSN CS de asserted time - 600 - - ns 1. see Figure 17. SPI timing diagram 2. see Figure 16. SO loading for disable time measurement Figure 16. SO loading for disable time measurement VDD SO 1 kΩ 1 kΩ +5 V 1.0 V 4.0 V tSOdis SO CS GADG0412170958PS Figure 17. SPI timing diagram t CSSO tSOCS tCSSCK t lead t SCKCS t SCKFSO CS SCK DIN DOUT DIN23 DOUT23 DOUT22 DOUT21 DOUT20 DOUT... DOUT... DOUT... DOUT0 DIN22 DIN21 DIN20 DIN... DIN... DIN1 DIN0 GADG0412171035PS L9177A Electrical characteristics DS12175 - Rev 5 page 24/55 |
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