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AT89C51ID2-RDTIM Datasheet(PDF) 89 Page - ATMEL Corporation |
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AT89C51ID2-RDTIM Datasheet(HTML) 89 Page - ATMEL Corporation |
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89 / 159 page  89 AT89C51ID2 4289A–8051–09/03 Figure 34. Format and State in the Master Receiver Mode SSLA R A Data 08h 40h 58h SSLA R AP W MT 10h 48h A or A continues 38h 38h A continues 68h Other master Other master 78h B0h To corresponding states in slave mode Successfull transmission to a slave receiver Next transfer started with a repeated start condition Not acknowledge received after the slave address Arbitration lost and addressed as slave A continues Other master n From master to slave From slave to master Any number of data bytes and their associated acknowledge bits This number (contained in SSCS) corresponds to a defined state of the 2-wire bus A Data P A 50h MR Arbitration lost in slave address or acknowledge bit Data A |
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