AT89C51ID2-RDTIM datasheet(14/159 Pages) ATMEL

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AT89C51ID2

4289A–8051–09/03

PI2.0 - PI2.1

34, 12

28, 6

1, 36

57, 26

Port I2: Port I2 is an open drain. It can be used as inputs (must be polar-

ized to Vcc with external resistor to prevent any parasitic current consump-

tion).

I/O

SCL (PI2.0): 2-wire Serial Clock

SCL output the serial clock to slave peripherals

SCL input the serial clock from master

I/O

SDA (PI2.1): 2-wire Serial Data

SDA is the bidirectional 2-wire data line

RST

Reset: A high on this pin for two machine cycles while the oscillator is run-

ning, resets the device. An internal diffused resistor to V

SS permits a power-

on reset using only an external capacitor to VCC. This pin is an output when

the hardware watchdog forces a system reset.

ALE/PROG

O (I)

Address Latch Enable/Program Pulse: Output pulse for latching the low

byte of the address during an access to external memory. In normal opera-

tion, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator

frequency, and can be used for external timing or clocking. Note that one

ALE pulse is skipped during each access to external data memory. This pin

is also the program pulse input (PROG) during Flash programming. ALE

can be disabled by setting SFR’s AUXR.0 bit. With this bit set, ALE will be

inactive during internal fetches.

PSEN

Program Strobe ENable: The read strobe to external program memory.

When executing code from the external program memory, PSEN is acti-

vated twice each machine cycle, except that two PSEN activations are

skipped during each access to external data memory. PSEN is not acti-

vated during fetches from internal program memory.

External Access Enable: EA must be externally held low to enable the

device to fetch code from external program memory locations 0000H to

FFFFH. If security level 1 is programmed, EA will be internally latched on

Reset.

Table 14. Pin Description (Continued)

Mnemonic

Pin Number

Type

Name and Function

PLCC44

VQFP44

PLCC68

VQFP64

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