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AT89C51ID2-RDTIM Datasheet(PDF) 25 Page - ATMEL Corporation |
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AT89C51ID2-RDTIM Datasheet(HTML) 25 Page - ATMEL Corporation |
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25 / 159 page  25 AT89C51ID2 4289A–8051–09/03 Table 21. CKCON1 Register CKCON1 - Clock Control Register (AFh) Reset Value = XXXX XXX0b Not bit addressable 7654 3210 ------- SPIX2 Bit Number Bit Mnemonic Description 7- Reserved 6- Reserved 5- Reserved 4- Reserved 3- Reserved 2- Reserved 1- Reserved 0 SPIX2 SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. |
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