SPEAR1340 datasheet(8/200 Pages) STMICROELECTRONICS

8 / 200 page

Device functions

SPEAr1340

8/200

Doc ID 023063 Rev 4

2.2

Multilayer interconnect matrix (BUSMATRIX)

The multilayer interconnect matrix is the connectivity infrastructure that enables data

exchange between the various blocks of the device. The BUSMATRIX supports parallel

communications between master and slave components, and ensures the maximum level of

system throughput.

Main features:

●

Hierarchical structure to meet the requirements of different system blocks and

peripherals:

–

high performance low latency

–

high performance medium latency

–

medium performance medium/long latency

–

slow peripherals and configurations

●

Power awareness through the power down request/acknowledgement of the power

management module

●

Single interrupt for outband signaling

2.3

Internal memories

SPEAr1340 integrates two embedded memories:

●

32 KB Boot ROM (BootROM)

●

Static RAM areas (SRAM)

2.3.1

BootROM

BootROM refers to the on-chip 32 KB ROM as well as the booting firmware pre-stored in

such memory. The supported booting devices are:

●

Serial NOR Flash

●

Parallel NOR Flash

●

NAND Flash

●

USB OTG

●

UART

●

SD/MMC

The BootROM firmware selects the booting device after reset by reading the status of the

STRAP[3:0] pins.

2.3.2

Static RAMs (SRAM)

A part of these memory areas is used during the bootstrap phase by BootROM firmware.

After booting, all SRAM areas are fully available for general purpose applications.

Main features:

●

32 KB of system RAM (SYSRAM0, single port)

When all power islands are switched off, SYSRAM0 loses its data content.

●

4 KB of Always-on RAM (SYSRAM1, single port)

When all power islands are switched off, SYSRAM1 maintains its data content.

SPEAR1340 Datasheet(PDF) 8 Page - STMicroelectronics

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