SPEAR1340 datasheet(9/200 Pages) STMICROELECTRONICS

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SPEAr1340

Device functions

Doc ID 023063 Rev 4

9/200

2.4

Multiport DDR controller (MPMC)

MPMC is a high-performance multichannel memory controller able to support DDR2 and

DDR3 memory devices. The multiport architecture ensures that memory is shared efficiently

among different high-bandwidth client modules.

Main features:

●

Supports both DDR3 and DDR2 devices; wide range of memory device cuts supported

up to 2 GB (Note: 1)

●

Two chip selects supported

●

Programmable memory data path size of full memory 32-bit data width or half memory

16-bit data width

●

Clock frequencies from 100 MHz to 533 MHz supported

●

6 AXI interfaces with a data interface width of 64 bits. Each port is configured with a

thread ID of 4 bits

●

Exclusive and locked accesses support

●

Weighted round-robin arbitration scheme support to ensure high memory bandwidth

utilization

●

DRAM command processing

●

A programmable register interface to control memory device parameters and protocols

including auto pre-charge

●

Full initialization of memory on memory controller reset

●

Automatically maps user addresses to the DRAM memory in a contiguous block

addressing starts at user address 0 and ends at the highest available address

according to the size and number of DRAM devices present

●

Fully pipelined command, read and write data interfaces to the memory controller

●

Advanced bank look-ahead features for high memory throughput

Note:

When the 2GB address space is enabled, the ACP function is not available.

2.5

Serial NOR Flash controller (SMI)

The serial NOR Flash controller integrated in SPEAr1340 acts as an AHB slave interface

(32-, 16- or 8-bit) to SPI-compatible off-chip memories. SMI allows the CPU to use these

serial memories either as data storage or for code execution.

Main features:

●

Supports a group of SPI-compatible Flash and EEPROM devices

●

Acts always as an SPI master and up to 2 SPI slave memory devices are supported

(through as many chip select signals), with up to 16 MB address space each.

●

The SMI clock signal (smi_clk_o) is generated by SMI (and inputs to all slaves) using a

clock provided by the AHB bus

●

smi_clk_o can be controlled by a programmable 7-bit prescaler allowing 127 different

clock frequencies.

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