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SPEAR1340 Datasheet(PDF) 146 Page - STMicroelectronics

Part # SPEAR1340
Description  Dual-core Cortex A9 HMI embedded MPU
PDF  200 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SPEAR1340 Datasheet(HTML) 146 Page - STMicroelectronics

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Electrical characteristics
SPEAr1340
146/200
Doc ID 023063 Rev 4
4.5
Voltage regulator characteristics
SPEAr1340 has three internal voltage regulators:
●
MIPHY single-lane regulator: the voltage controlled by this regulator is internally
connected to the MIPHY supply, but it is also externally visible on
MIPHY0_VDD2PLL2V5. The regulator is always active; it is not possible to bypass it.
●
VREG1 regulator: used only for USB
●
VREG2 regulator: used for all PLLs (PLL1, PLL2, PLL3, DDR PLL), ADC and OTP.
Each regulator receives a 3V3 voltage supply as input and generates a 2V5 voltage supply
as output.
The following table shows the main requirements for the voltage regulators.
4.6
MiPHY characteristics
For SATA operation, the MIPHY0_XTAL1/MIPHY0_XTAL2 clock input can be implemented
by a 25 MHz crystal oscillator. For PCIe operation, a suitable clock driver such as ON
Semiconductor NB3N5573 or Silicon labs Si5330C_A000207 can be used.
Table 54.
Voltage regulators requirements
Voltage regulator input
Voltage regulator output
Balls
connected
Input
voltage
Output
voltage
Max
current
External
capacitor
MIPHY0_VREG_3V3_IN
MIPHY0_VDD2PLL2V5
P3
3.3 V
2.5 V
100 mA
10
μF
VREG1_3V3_IN
VREG1_2V5_OUT (ball M6) J4 E3 G3
3.3 V
2.5 V
150 mA
2.2
μF
VREG2_3V3_IN
VREG2_2V5_OUT (ball F6)
E6 E4 N5
AC5 U19 C4
3.3 V
2.5 V
150 mA
2.2
μF
Table 55.
MiPHY characteristics
Symbol
Parameter
Min
Typ
Max
Unit
fOSC
MIPHY0_XTAL1/MIPHY0_XTAL2 clock
input frequency for SATA configuration
25
MHz
MIPHY0_XTAL1/MIPHY0_XTAL2 clock
input frequency for PCIe configuration
100
VIH
MIPHY0_RXp/MIPHY0_RXn differential
input HIGH voltage
+150
mV
VIL
MIPHY0_RXp/MIPHY0_RXn differential
input LOW voltage
-150
mV
VIN(OSC)
MIPHY0_XTAL1/MIPHY0_XTAL2 clock
input voltage
-0.3
1.15
V
ZIN(OSC)
MIPHY0_XTAL1/MIPHY0_XTAL2 clock
input impedance
50
Ω



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