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SPEAR1340 Datasheet(PDF) 157 Page - STMicroelectronics

Part # SPEAR1340
Description  Dual-core Cortex A9 HMI embedded MPU
PDF  200 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SPEAR1340 Datasheet(HTML) 157 Page - STMicroelectronics

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SPEAr1340
Timing characteristics
Doc ID 023063 Rev 4
157/200
5.6
FSMC timing characteristics
This section describes the timing characteristics of the flexible static memory controller. The
FSMC can interface NAND Flash, NOR and SRAM. All the possible scenarios are described
below.
The timing characterization is performed assuming an output load capacitance of 10 pF on
all outputs.
5.6.1
NAND Flash configuration timing characteristics
Figure 21.
NAND Flash configuration timing waveform
TALE, TCLE, TW, TR and TD are fixed values: they depend only on the internal timings of
SPEAr.
TSET, THOLD, TWAIT and THIZ are programmable timings defined by FSMC registers. They
can be calculated as:
TSET = (Set + 1) * THCLK (min value for Set is 0)
TWAIT = (Wait + 1) * THCLK (min value for Wait is 1)
THOLD = (Hold + 1) * THCLK (min value for Hold is 1)
THIZ = Hiz * THCLK (min value for Hiz is 0)
THCLK = 6 ns (period of the AHB clock, the FSMC input clock)
TMEM is the output delay of the NAND Flash.
When writing a data, since the NAND Flash strobes it on the rising edge of FSMC_WEn, the
user should choose the correct values of Set, Wait, Hold and Hiz in order to satisfy the
following constraints:
TSET + TW + TWAIT - THIZ - TD ≥ TSETUP (NAND_FLASH)
THOLD + TW - THCLK + TD ≥ THOLD (NAND_FLASH)
FSMC_CExn
FSMC_ALE_AD17
tHCLK - tALE
FSMC_WEn
FSMC_CLE_AD16
FSMC_IO (ouT)
DATAOUT
FSMC_REn
FSMC_IO (in)
DATAIN
tWAIT
tSET + tW
tHIZ + tD
tHCLK - tD
tHOLD + tW
TWAIT
tSET + tR
tHOLD + tR
tMEM
tMEM
tHCLK - tCLE



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