28

AT45DB321D [DATASHEET]

3597R–DFLASH–11/2012

14.

Power-on/Reset State

When power is first applied to the device, or when recovering from a reset condition, the device will default to Mode 3. In

addition, the output pin (SO) will be in a high-impedance state, and a high-to-low transition on the CS pin will be required to start

a valid instruction. The mode (Mode 3 or Mode 0) will be automatically selected on every falling edge of CS by sampling the

inactive clock state.

14.1

Initial Power-up/Reset Timing Restrictions

selected in order to perform a read operation.

perform a write (program or erase) operation. After initial power-up, the device will default to standby mode.

Table 14-1. Initial Power-up/Reset Timing Restrictions

15.

System Considerations

The RapidS serial interface is controlled by the SCK clock, SI serial input, and CS chip select pins. These signals must rise and

fall monotonically and be free from noise. Excessive noise or ringing on these pins can be misinterpreted as multiple edges and

cause improper operation of the device. The PC board traces must be kept to a minimum distance or appropriately terminated

to ensure proper operation. If necessary, decoupling capacitors can be added on these pins to provide filtering against noise

glitches.

As system complexity continues to increase, voltage regulation is becoming more important. A key element of any voltage

regulation scheme is its current sourcing capability. Like all flash memories, the peak current for a DataFlash device occurs

during the programming and erase operation. The regulator needs to supply this peak current requirement. An under-specified

regulator can cause current starvation. Besides increasing system noise, current starvation during programming or erase can

lead to improper operation and possible data corruption.

Symbol

Parameter

Min

Typ

Max

Unit

70

μs

Power-up device delay before write allowed

20

ms

Power-on reset voltage

1.5

2.5

V