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AT45DB321D Datasheet(PDF) 4 Page - Analog Devices

Part # AT45DB321D
Description  32Mb, 2.5V or 2.7V DataFlash
PDF  51 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AT45DB321D Datasheet(HTML) 4 Page - Analog Devices

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AT45DB321D [DATASHEET]
3597R–DFLASH–11/2012
Figure 1-2. Block Diagram
2.
Memory Array
To provide optimal flexibility, the AT45DB321D memory array is divided into three levels of granularity comprising sectors,
blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level, and details the number of
pages per sector and block. All program operations to the DataFlash device occur on a page-by-page basis. The erase
operations can be performed at the chip, sector, block, or page level.
Figure 2-1. Memory Architecture Diagram
Flash Memory Array
Page (512-/528-bytes)
Buffer 2 (512-/528-bytes)
Buffer 1 (512-/528-bytes)
I/O Interface
SCK
CS
RESET
VCC
GND
RDY/BUSY
WP
SO
SI
SECTOR 0a = 8 Pages
4,096-/4,224-bytes
SECTOR 0b = 120 Pages
61,440-/63,360-bytes
Block = 4,096-/4,224-bytes
8 Pages
SECTOR 0a
Page = 512-/528-bytes
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
PAGE 8,190
PAGE 8,191
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
Sector Architecture
Block Architecture
Page Architecture
BLOCK 0
BLOCK 1
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
BLOCK 1,022
BLOCK 1,023
BLOCK 126
BLOCK 127
BLOCK 128
BLOCK 129
SECTOR 63 = 128 Pages
65,536-/67,586-bytes
BLOCK 2
SECTOR 1 = 128 Pages
65,536-/67,584-bytes
SECTOR 62 = 128 Pages
65,536-/67,584-bytes
SECTOR 2 = 128 Pages
65,536-/67,584-bytes



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