17

AT45DB321D [DATASHEET]

3597R–DFLASH–11/2012

8.2.1

Programming the Security Register

The user programmable portion of the security register does not need to be erased before it is programmed.

To program the security register, the CS pin must first be asserted, and then the appropriate four-byte opcode sequence must

be clocked into the device in the correct order. The four-byte opcode sequence must start with 9BH, and be followed by 00H,

00H, and 00H. After the last bit of the opcode sequence has been clocked into the device, the data for the content of the 64-byte

user programmable portion of the security register must be clocked in.

After the last data byte has been clocked in, the CS pin must be deasserted to initiate the internally self-timed program cycle.

that the device is busy. If the device is powered down during the program cycle, then the contents of the 64-byte user

programmable portion of the security register cannot be guaranteed.

If the full 64 bytes of data are not clocked in before the CS pin is deasserted, then the values of the byte locations not clocked in

cannot be guaranteed. For example, if only the first two bytes are clocked in instead of the complete 64 bytes, then the

remaining 62 bytes of the user programmable portion of the security register cannot be guaranteed. Furthermore, if more than

64 bytes of data are clocked into the device, then the data will wrap back around to the beginning of the register. For instance, if

The user programmable portion of the security register can be programmed only once. Therefore, it is not possible to program

only the first two bytes of the register and then program the remaining 62 bytes at a later time.

The program security register command utilizes the internal SRAM buffer 1 for processing. Therefore, the contents of buffer 1

will be altered from its previous state when this command is issued.

Figure 8-3. Program Security Register

8.2.2

Reading the Security Register

The security register can be read by first asserting the CS pin and then clocking in an opcode of 77H, followed by three dummy

bytes. After the last don't care bit has been clocked in, the content of the security register can be clocked out on the SO pin.

After the last byte of the security register has been read, additional pulses on the SCK pin will simply result in undefined data

being output on the SO pin.

Deasserting the CS pin will terminate the read security register operation and put the SO pin into a high-impedance state.

Figure 8-4. Read Security Register

Data byte

n

Opcode

byte 1

Opcode

byte 2

Opcode

byte 3

Opcode

byte 4

Data byte

n + 1

Data byte

n + x

CS

Each transition

represents 8 bits

SI

Opcode

X

X

X

Data byte

n

Data byte

n + 1

CS

Data byte

n + x

Each transition

represents 8 bits

SI

SO