PCDC1008-R215EMO datasheet(21/51 Pages) IRF

21 / 51 page

IR3447

www.irf.com

July 17, 2013

Automatic restart is initiated when the sensed

temperature drops within the operating range. There

is a 20

oC hysteresis in the thermal shutdown

threshold.

REMOTE VOLTAGE SENSING

True differential remote sensing in the feedback loop

is critical to high current applications where the output

voltage across the load may differ from the output

voltage measured locally across an output capacitor

at the output inductor, and to applications that require

die voltage sensing.

The RS+ and RS- pins of the IR3447 form the inputs

to a remote sense differential amplifier (RSA) with

high speed, low input offset and low input bias current

which ensure accurate voltage sensing and fast

transient response in such applications.

The input range for the differential amplifier is limited

to 1.5V below the VCC rail.

Note that IR3447

incorporates a smart LDO which switches the VCC rail

voltage depending on the loading. When determining

the input range assume the part is in light load and

using the lower VCC rail voltage.

There are two remote sense configurations that are

usually implemented.

Figure 10 shows a general

remote sense (RS) configuration. This configuration

allows the RSA to monitor output voltages above

VCC. A resistor divider is placed in between the

output and the RSA to provide a lower input voltage to

the RSA inputs.

Typically, the resistor divider is

calculated to provide VREF (0.6V) across the RSA

inputs which is then outputted to RSo.

The input

impedance of the RSA is 63 KOhms typically and

should be accounted for when determining values for

the resistor divider. To account for the input

impedance, assume a 63 KOhm resistor in parallel to

the lower resistor in the divider network.

The

compensation is then designed for 0.6V to match the

RSo value.

Low voltage applications can use the second remote

sense configuration. When the output voltage range

is within the RSA input specifications, no resistor

divider is needed in between the converter output and

RSA. The second configuration is shown in Figure

11. The RSA is used as a unity gain buffer and

compensation is determined normally.

(< VCC-1.5V)

RSA

RS+

RS-

RSo

Vout

Resistor Divider

Figure 10: General Remote Sense Configuration

Figure 11: Remote Sense Configuration for Vout less

than VCC-1.5V

EXTERNAL SYNCHRONIZATION

IR3447 incorporates an internal phase lock loop (PLL)

circuit which enables synchronization of the internal

oscillator to an external clock. This function is

important to avoid sub-harmonic oscillations due to

beat frequency for embedded systems when multiple

point-of-load (POL) regulators are used. A multi-

function pin, Rt/Sync, is used to connect the external

clock. If the external clock is present before the

converter turns on, Rt/Sync pin can be connected to

the external clock signal solely and no other resistor is

needed. If the external clock is applied after the

converter turns on, or the converter switching

frequency needs to toggle between the external clock

frequency and the internal free-running frequency, an

external resistor from Rt/Sync pin to LGnd is required

to set the free-running frequency.

When an external clock is applied to Rt/Sync pin after

the converter runs in steady state with its free-running

frequency,

transition

from

the

free-running

frequency to the external clock frequency will happen.

This transition is to gradually make the actual

switching frequency equal to the external clock

frequency, no matter which one is higher. When the

external clock signal is removed from Rt/Sync pin, the

switching frequency is also changed to free-running

gradually. In order to minimize the impact from these

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