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PCDC1008-R215EMO Datasheet(PDF) 31 Page - International Rectifier

Part # PCDC1008-R215EMO
Description  25A Highly Integrated SupIRBuck Single-Input Voltage, Synchronous Buck Regulator
PDF  51 Pages
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Manufacturer  IRF [International Rectifier]
Direct Link  http://www.irf.com
Logo IRF - International Rectifier

PCDC1008-R215EMO Datasheet(HTML) 31 Page - International Rectifier

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IR3447
31
www.irf.com
© 2013 International Rectifier
July 17, 2013
to the RSA, β = 1. Please refer to the Remote
Sensing Amplifier section)
Lo
= 0.215 µH
Co = 10 x 47µF, ESR≈3mΩ each
It must be noted here that the value of the
capacitance used in the compensator design must be
the small signal value. For instance, the small signal
capacitance of the 47µF capacitor used in this design
is 25.7µF at 1.2 V DC bias and 600 kHz frequency. It
is this value that must be used for all computations
related to the compensation. The small signal value
may be obtained from the manufacturer’s datasheets,
design tools or SPICE models. Alternatively, they may
also be inferred from measuring the power stage
transfer function of the converter and measuring the
double pole frequency FLC and using equation (20) to
compute the small signal Co.
These result to:
FLC = 21.4 kHz
FESR = 2.06 MHz
Fs/2 = 300 kHz
Select crossover frequency F0=100 kHz
Since FLC<F0<Fs/2<FESR, Type III is selected to place
the pole and zeros.
Detailed calculation of compensation Type III:
Desired Phase Margin Θ = 70°
sin
1
sin
1
2
o
Z
F
F
17.6 kHz
sin
1
sin
1
2
o
P
F
F
567.1 kHz
Select:
2
1
5
.
0
Z
Z
F
F
8.8 kHz and
s
P
F
F
5
.
0
3
300 kHz
Select C4 = 2.2nF.
Calculate R3, C3 and C2:
in
osc
o
o
o
V
C
V
C
L
F
R
4
3
2
; R3 = 2.37 kΩ,
Select: R3 = 1.91 kΩ
3
1
3
2
1
R
F
C
Z
; C3 = 7.5 nF,
Select: C3 = 8.2 nF
3
3
2
2
1
R
F
C
P
; C2 = 221 pF,
Select: C2 = 160 pF
Calculate R4, R5 and R6:
2
4
4
2
1
P
F
C
R
; R4 = 127.6 Ω,
Select R4 = 127 Ω
2
4
5
2
1
Z
F
C
R
; R5 = 4.11 kΩ,
Select R5 = 4.22 kΩ
5
6
R
V
V
V
R
ref
o
ref
; R6 = 4.11 kΩ,
Select R6 = 4.22 kΩ
If (β x Vo) equals Vref, R6 is not used.
Setting the Power Good Threshold
In this design IR3447, the PGood outer limits are set
at 95% and 120% of VREF. PGood signal is asserted
1.3ms after Vsns voltage reaches 0.95*0.6V=0.57V
(Figure 28)
. As long as the Vsns voltage is between
the threshold ranges, Enable is high, and no fault
happens, the PGood remains high.
The following formula can be used to set the PGood
threshold. Vout (PGood_TH) can be taken as 95% of Vout.
Choose Rsns1=4.22 KΩ.



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