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Z8018233FSC Datasheet(PDF) 91 Page - Zilog, Inc. |
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Z8018233FSC Datasheet(HTML) 91 Page - Zilog, Inc. |
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91 / 109 page  3-91 Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL PRELIMINARY Zilog DS971820600 Z8S180 AC CHARACTERISTICS Table A. Z8L180 and Z8S180 Timings Z8L180 Z8S180 20 MHz 33 MHz No. Sym Parameter Min Max Min Max Unit Note 1 tcyc Clock Cycle Time 50 2000 30 2000 ns [1] 2 tCHW Clock Pulse Width (High) 15 10 ns [1] 3 tCLW Clock Pulse Width (Low) 15 10 ns [1] 4 tcf Clock Fall Time 10 5 ns [1] 5 tcr Clock Rise Time 10 5 ns [1] 6 tAD Address Valid from Clock Rise 15 15 ns 7 tAS Address Valid to /MREQ, /IORQ, /MRD Fall 5 5 ns 8 tMED1 Clock Fall to /MREQ Fall Delay 15 10 ns 9 tRDD1 Clock Fall to /RD, /MRD (/IOC=1) 25 15 ns Clock Rise to /RD, /MRD Fall (/IOC=0) 35 15 ns 10 tM1D1 Clock Rise to /M1 Fall delay 35 15 ns 11 tAH Address Hold time (/MREQ, /IORQ, /RD, /WR/MRD) 5 5 ns 12 tMED2 Clock Fall to /MREQ Rise Delay 25 15 ns 13 tRDD2 Clock Fall to /RD, /MRD Rise Delay 25 15 ns 14 tM1D2 Clock Rise to /M1 Rise Delay 40 15 ns 15 tDRS Data Read Setup Time 15 15 ns 16 tDRH Data Read Hold Time 0 0 ns 17 tSTD1 Clock Edge to ST Fall 30 15 ns 18 tSTD2 Clock Edge to ST Rise 30 15 ns 19 tWS /WAIT Setup Time to Clock Fall 15 10 ns [2] 20 tWH /WAIT Hold Time from Clock Fall 10 5 ns 21 tWDZ Clock Rise to Data Float Delay 35 20 ns 22 tWRD1 Clock Rise to /WR,/MWR Fall Delay 25 15 ns 23 tWDD Clock Fall to Write Data Delay 25 15 ns 24 tWDS Write Data Setup Time to /WR,/MWR Fall 10 10 ns 25 tWRD2 Clock Fall to /WR Rise 25 15 ns 26 tWRP /WR Pulse Width (Memory Write Cycles) 75 45 ns 26a /WR Pulse Width (I/O Write Cycles) 130 70 ns 27 tWDH Write Data Hold Time from /WR Rise 10 5 ns 28 tIOD1 Clock Fall to /IORQ Fall Delay (/IOC=1) 25 15 ns Clock Rise to /IORQ Fall Delay (/IOC=0) 25 15 ns 29 tIOD2 Clock Fall /IOQR Rise Delay 25 15 ns 30 tIOD3 /M1 Fall to /IORQ Fall Delay 100 80 ns 31 tINTS /INT Setup Time to Clock Fall 20 15 ns 32 tINTH /INT Hold Time from Clock Fall 10 10 ns 33 tNMIW /NMI Pulse Width 35 25 ns 34 tBRS /BUSREQ Setup Time to Clock Fall 10 10 ns 35 tBRH /BUSREQ Hold Time from Clock Fall 10 10 ns 36 tBAD1 Clock Rise to /BUSACK Fall Delay 25 15 ns 37 tBAD2 Clock Fall to /BUSACK Rise Delay 25 15 ns 38 tBZD Clock Rise to Bus Floating Delay Time 40 30 ns 39 tMEWH /MREQ Pulse Width (High) 35 25 ns 40 tMEWL /MREQ Pulse Width (Low) 35 25 ns |
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