Z8018233FSC datasheet(68/109 Pages) ZILOG

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3-68

Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

PRELIMINARY

Zilog

DS971820600

Transmit And Receive Timers (Continued)

When a write from the PC/XT/AT is made to the Transmit

Holding Register, an interrupt to the Z180 MPU is generated.

The Z180 MPU then reads the data in the Transmit Holding

the time constant from the Transmitter Time Constant

the count. After the timer reaches a count of zero the

Transmit Holding Register Empty bit is set. However, the

above is only true when the PC/XT/AT is reading the

Transmit Holding Register Empty bit. To allow the Z180

MPU to know that it has already read the byte of data,

immediately following a read from the Transmit Holding

is set. This mirrored bit is always read back to the Z180

MPU when it reads the Line Status Register.

If the transmitter timer is not enabled when the Z180 MPU

reads the Transmit Holding Register, both Transmit Holding

operation, the effect is similar as the status to PC is always

delayed such that a PC interrupt for empty FIFO will not

occur before the time required for each character read

from the FIFO by the Z180 has elapsed. The effect is that

the PC will not see data requests from an empty FIFO any

faster than would occur with a true UART when the delay

feature is enabled. This timer is also used to delay data

transfer for TSR buffer to Z80182 THR in double buffer

mode.

111111

Receiver Time Constant

Figure 68. Receive Time Constant Register

(Z180 MPU Read/Write, Address xxFBH)

When the Z180™ MPU writes to the Receive Buffer register

and the Receive Timer is enabled, the Receive Timer is

loaded with the Receive Time Constant, the timer is enabled

and counts down to zero. When the timer reaches zero, the

Data Ready bit in the Line Status Register is set. As with the

Transmit Timer, the Data Ready bit is also mirrored.

Immediately upon a write to the Receive Buffer, the mirrored

bit is set to let the Z180 MPU know that the byte has already

been written. If the timer is not enabled, then both Data

Ready bits are set immediately upon a write to the Receive

Buffer. The FIFO mode of operation is similar in that the

status to the PC is always delayed by the time required for

each character written to the FIFO by the Z180. The effect

is that the PC will not see a FIFO trigger level or DMA

request faster than would occur with a true UART when the

delay feature is enabled.

Z8018233FSC Datasheet(PDF) 68 Page - Zilog, Inc.

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