Z87200 datasheet(11/54 Pages) ZILOG

11 / 54 page

Z87200

Zilog

Spread-Spectrum Transceiver

DS96WRL0400

4-11

A.C. CHARACTERISTICS - RECEIVER

Operating Conditions: VDD = 5.0V ±5%, VSS = 0V

TA = 0° to +70°C

Symbol

Parameter

Min

Max.

Units

Conditions

RXIFCLK

RXIFCLK Frequency

45.056

20.0

MHz

Z8720045FSC

Z8720020FSC

tCH

RXIFCLK Pulse

width, High

tCL

RXIFCLK Pulse

width, Low

tSU

RXIIN or RXQIN to

RXIFCLK setup

3ns

tHD

RXIIN or RXQIN to

RXIFCLK hold

7ns

tCR

RXIFCLK to

RXSPLPLS,

RXSYMPLS, or

/RXDRDY delay

tCD

RXIFCLK to RXOUT,

RXIOUT, or

RXQOUT delay

Notes:

1. The number of RXIFCLK cycles per cycle of RXSPLPLS is determined by the data stored in bits 5-0

of address 02H. It is shown as 2 in Figure 9, but can be set from 2 to 64.

2. The rising edge of /RXDRDY should be used to clock out the data (RXOUT, RXIOUT, or RXQOUT).

Z87200 Datasheet(PDF) 11 Page - Zilog, Inc.

Z87200 Datasheet(HTML) 11 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

Datasheet Download

Link URL