Z87200 datasheet(30/54 Pages) ZILOG

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Z87200

Spread-Spectrum Transceiver

Zilog

4-30

DS96WRL0400

CONTROL REGISTERS (Continued)

ficients, each requiring 2 bits of storage according to the

mapping shown in Table 8.

As a convention, Tap 0 is the first tap as the received sig-

nal enters the PN Matched Filter, and Tap 63 is the last. All

active taps of the PN Matched Filter, from Tap 0 up to Tap

(N-1), where N is the length of the PN code, should be pro-

grammed with tap coefficient values of +1 or -1 according

to the PN code sequence. Setting the end coefficients of

the PN Matched Filter registers to zero values permits the

effective length of the filter to be made shorter than 64

taps.

Addresses 07H through 16H:

Matched Filter Acquisition/Preamble Symbol

Coefficients

Addresses 07H to 16H contain the 64 2-bit Acquisition/Pre-

amble PN code coefficient values. The 128 bits of informa-

tion are stored in 16 8-bit registers at addresses 07H to 16H

as shown in Table 8.

Addresses 17H through 26H:

Matched Filter Data Symbol Coefficients

Addresses 17H to 26H contain the 64 2-bit Data Symbol

PN code coefficient values. The 128 bits of information are

stored in 16 8-bit registers at addresses 17H to 26H as

shown in The contents of addresses 17H to 26H are inde-

pendent of and not affected by the contents of addresses

07H to 16H.

Address 27H:

Bit 0 — Front End Processor Disable

The Front End Processor (FEP) averages the two base-

band samples per chip by adding consecutive pairs of

samples. The function may be disabled for test purposes

by using this bit: when set low, the FEP is enabled and in

its normal mode of operation; when set high, the FEP is

disabled.

Power Estimator Registers

Address 28H:

Bits 1-0 — Matched Filter Viewport Control

The Z87200 incorporates viewport (data selector) circuitry

to select any eight consecutive bits from the 10-bit outputs

of the PN Matched Filter as the 8-bit inputs to the Power

Estimator and DPSK Demodulator blocks. The Symbol

Tracking Processor, however, operates on the full 10-bit

PN Matched Filter outputs before the viewport is applied.

The signal levels of the PN Matched Filter output reflect

the number of chips per symbol and the signal-to-noise ra-

tio of the signal. Setting the viewport thus effectively nor-

malizes the PN Matched Filter outputs prior to further pro-

cessing. The unsigned value, n, of bits 1-0 of address 28H

determines the 8-bit input to the Power Estimator and

DPSK Demodulator blocks as the 10-bit PN Matched Filter

output divided by 2n. Equivalently, bits 1-0 control the

viewport of the PN Matched Filter output as shown in Note

Table 8. PN Matched Filter Tap Values

Tap Bits 1,0

Tap Coeff

-1

Table 9. Acquisition/Preamble Coefﬁcient Storage

Address 16H

Bits 7,6

Bits 5,4

Bits 3,2

Bits 1,0

Coeff. 63

Coeff. 62

Coeff. 61

Coeff. 60

Address 15H

Bits 7,6

Bits 5,4

Bits 3,2

Bits 1,0

Coeff. 59

Coeff. 58

Coeff. 57

Coeff. 56

- - -

Address 08H

Bits 7,6

Bits 5,4

Bits 3,2

Bits 1,0

Coeff. 7

Coeff. 6

Coeff. 5

Coeff. 4

Address 07H

Bits 7,6

Bits 5,4

Bits 3,2

Bits 1,0

Coeff. 3

Coeff. 2

Coeff. 1

Coeff. 0

Table 10. Data Symbol Coefﬁcient Storage

Address 26H

Bits 7,6

Bits 5,4

Bits 3,2

Bits 1,0

Coeff. 63

Coeff. 62

Coeff. 61

Coeff. 60

Address 25H

Bits 7,6

Bits 5,4

Bits 3,2

Bits 1,0

Coeff. 59

Coeff. 58

Coeff. 57

Coeff. 56

- - -

Address 18H

Bits 7,6

Bits 5,4

Bits 3,2

Bits 1,0

Coeff. 7

Coeff. 6

Coeff. 5

Coeff. 4

Address 17H

Bits 7,6

Bits 5,4

Bits 3,2

Bits 1,0

Coeff. 3

Coeff. 2

Coeff. 1

Coeff. 0

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