• 3.3V to 12V input voltage1

• 20A maximum load capability, with no derating up to T

• 5 bit DAC settable, 0.925V to 2V output voltage range 2

• Configurable down to 3.3Vin & up to 3.3Vout with simple external circuit 3

• 200kHz or 300kHz nominal switching frequency

• Optimized for very low power losses

• Over & undervoltage protection

• Adjustable lossless current limit

• Internal features minimize layout sensitivity *

• Very small outline 14mm x 14mm x 3mm

Full Function Synchronous Buck Power Block

Integrated Power Semiconductors, Control IC & Passives

The iP1001 is a fully optimized solution for high current synchronous buck applications requiring up to 20A.

The iP1001 is optimized for single-phase applications, and includes a full function fast transient response

PWM control, with an optimized power semiconductor chip-set and associated passives, achieving benchmark

power density. Very few external components are required, including output inductor, input & output capacitors.

Further range of operation to 3.3Vin can be achieved with the addition of a simple external boost circuit, and

operation up to 3.3Vout can be achieved with a simple external voltage divider.

iPOWIR technology offers designers an innovative board space-saving solution for applications requiring high

power densities. iPOWIR technology eases design for applications where component integration offers

benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for layout,

heat transfer and component selection.

Description

iP1001 Power Block

Features

* Although, all of the difficult PCB layout and bypassing issues have been addressed with the internal design of the iPOWIR block, proper layout techniques should be

applied for the design of the power supply board. There are no concerns about unwanted shutdowns common to switching power supplies, if operated as specified. The

iPOWIR block will function normally, but not optimally without any additional input decoupling capacitors. Input decoupling capacitors should be added at Vin pin for stable

and reliable long term operation. No additional bypassing is required on the Vdd pin. See layout guidelines in datasheet for more detailed information.

PD - 94336c

05/20/03

iP1001

www.irf.com

1

iP1001 Internal Block Diagram

GNDS

SGND

PGND

PWM

& Driver

D0

D1

D2

D3

D4

ENABLE

PGOOD

5 Bit

DAC

ILIM

FREQ

GNDS

SGND

PGND

PWM

& Driver

D0

D1

D2

D3

D4

ENABLE

PGOOD

5 Bit

DAC

ILIM

FREQ