IP1001 datasheet(10/18 Pages) IRF

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iP1001

iP1001 User’s Design Guidelines

The iP1001 is a 20A power block that consists of

optimized power semiconductors, PWM control and

its associated passive components. It is based on

a synchronous buck topology and offers an optimized

solution where space, efficiency and noise caused

by stray parasitics are of concern. The iP1001 com-

ponents are integrated in a ball grid array (BGA) pack-

age where the electrical and thermal conduction is

accomplished through solder balls.

FUNCTIONAL DESCRIPTION

The standard iP1001 operating input voltage range

is 5V to 12V. The input voltage can also be easily

configured to run at voltages down to 3.3V.

FREQ

The PWM control is pseudo current mode. The ESR

of the output filter capacitor is used for current sens-

ing and the output voltage ripple developed across

the ESR provides the PWM ramp signal.

iP1001 offers two switching frequency settings,

200kHz and 300kHz. At a given setting the switching

frequency will remain relatively constant indepen-

dent of load current.

DD (+5V bias)

An external 5V bias supply is required to operate the

iP1001. In applications where input voltages are

lower than 4.5V, and where 5V is not available, a

special boost circuit is required to supply V

DD with 5V

(as shown in the reference design).

Soft Start, V

DD Undervoltage Lockout

When V

DD rises above 4.2V a soft start is initiated by

ramping the maximum allowable current limit. The

ramp time is typically 1.8ms. An external capacitor

can be added across the current limit resistor from

ILIM to PGND to provide up to 5ms ramp time. Select

the capacitor according to the 10nf/ms rule.

PGOOD

The PGOOD comparator constantly monitors V

F for

undervoltage. A 5% drop in output voltage can cause

PGOOD to go low. PGOOD pin is internally pulled-

up to V

DD through a 100K, 5% resistor. If it is desired

to use the PGOOD signal to enable another stage

using iP1001, then it is recommended to filter and

buffer PGOOD to prevent transients appearing at

the output from pulling PGOOD low.

OVP (Output Overvoltage Protection)

If the overvoltage trip 2.25V threshold is reached, the

OVP is triggered, the circuit is shutdown and the

bottom FET is latched on discharging the output filter

capacitor. Pulling ENABLE low resets the latch. The

overvoltage trip threshold is scaled accordingly, if

output voltages greater than 2V are set through

voltage dividers.

UVP (Output Undervoltage Protection)

The Output Undervoltage Protection trip threshold is

fixed at 0.8V. If ENABLE is pulled up and V

F is below

0.8V for a duration of 10-20ms, the PWM will be in a

latched state, with the bottom FET latched on, and

will not restart until ENABLE is recycled.

DAC Converter (D0-D4)

The output voltage is programmed through a 5-bit

DAC (see the VID code in table 1). The output volt-

age can be programmed from 0.925V to 2V. To elimi-

nate external resistors, the DAC pins are internally

pulled up. To set for output voltages above 2V, the

DAC must be set to 2V and a resistor divider,

R3 & R4 (see Fig 10.), is used. The values of the

resistors are selected using equation 1.

Equation 1 :

Vout = V

F x (1 + R3/R4)

where V

F is equal to the DAC setting

and R4 is recommended to be ~1k

Ω

Table 3 - iP1001 Operating Truth Table

ENABLE

Bottom

FET

Mode

Com ments

Low

Shutdown

High

OFF

Shutdown

DAC code = X1111, Both FETs

are turned OFF.

High

Switching

PW M (Running)

High

Fault

Fault latch set by OVP or UVP.

This mode will sustain until VDD

is cycled or ENABLE is reset.

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