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TNETV1647GSTZWT Datasheet(PDF) 109 Page - Texas Instruments |
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TNETV1647GSTZWT Datasheet(HTML) 109 Page - Texas Instruments |
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109 / 236 page  TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 6.6 Clock PLLs There are two independently controlled PLLs on DM6441. PLL1 generates the frequencies required for the DSP, ARM, VICP, DMA, VPFE, and other peripherals. PLL2 generates the frequencies required for the DDR2 interface and the VPBE in certain modes. The recommended reference clock for both PLLs is the 27-MHz crystal input. The USB2.0 PHY contains a third PLL embedded within it and the 24-MHz oscillator is its reference clock source. This particular PLL is only usable for USB operation, and is discussed further in the TMS320DM644x DMSoC Universal Serial Bus (USB) Controller User's Guide (literature number SPRUE35). See also the TMS320DM644x DMSoC Peripherals Overview Reference Guide (literature number SPRUE19). A summary of the PLL controller registers is shown in Table 6-12. For more details, see the TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14). Table 6-12. PLL and Reset Controller Registers Memory Map HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION PLL1 Controller Registers 0x01C4 0800 PID Peripheral Identification and Revision Information Register 0x01C4 08E4 RSTYPE Reset Type Register 0x01C4 0900 PLLCTL PLL Controller 1 Operations Control Register 0x01C4 0910 PLLM PLL Controller 1 Multiplier Control Register 0x01C4 0918 PLLDIV1 PLL Controller 1 Control-Divider 1 Register (SYSCLK1) 0x01C4 091C PLLDIV2 PLL Controller 1 Control-Divider 2 Register (SYSCLK2) 0x01C4 0920 PLLDIV3 PLL Controller 1 Control-Divider 3 Register (SYSCLK3) 0x01C4 0928 POSTDIV PLL Controller 1 Post-Divider Control Register 0x01C4 092C BPDIV PLL Controller 1 Bypass Control-Divider Register (SYSCLKBP) 0x01C4 0938 PLLCMD PLL Controller 1 Command Register 0x01C4 093C PLLSTAT PLL Controller 1 Status Register (Shows PLLCTRL Status) PLL Controller 1 Alignment Control Register 0x01C4 0940 ALNCTL (Indicates Which SYSCLKs Need to be Aligned for Proper Device Operation) PLL Controller 1 Divider Change Register 0x01C4 0944 DCHANGE (Indicates if SYSCLK Divide Ratio has Been Modified) 0x01C4 0948 CKEN PLL Controller 1 Clock Enable Register 0x01C4 094C CKSTAT PLL Controller 1 Clock Status Register (For All Clocks Except SYSCLKx) 0x01C4 0950 PLL Controller 1 System Clock Status 1 Register (Indicates SYSCLK on/off SYSTAT Status) 0x01C4 0960 PLLDIV4 PLL Controller 1 Control-Divider 4 Register (SYSCLK4) 0x01C4 0964 PLLDIV5 PLL Controller 1 Control-Divider 5 Register (SYSCLK5) 0x01C4 0C00 PID Peripheral Identification and Revision Information Register 0x01C4 0D00 PLLCTL PLL Controller 2 Operations Control Register 0x01C4 0D10 PLLM PLL Controller 2 Multiplier Control Register 0x01C4 0D18 PLLDIV1 PLL Controller 2 Control-Divider 1 Register (SYSCLK1) 0x01C4 0D1C PLLDIV2 PLL Controller 2 Control-Divider 2 Register (SYSCLK2) 0x01C4 0D20 - 0x01C4 0D2B POSTDIV PLL Controller 2 Post-Divider Control Register 0x01C4 0D2C BPDIV PLL Controller 2 Bypass Control-Divider Register (SYSCLKBP) 0x01C4 0D38 PLLCMD PLL Controller 2 Command Register 0x01C4 0D3C PLLSTAT PLL Controller 2 Status Register (Shows PLLCTRL Status) PLL Controller 2 Alignment Control Register 0x01C4 0D40 ALNCTL (Indicates Which SYSCLKs Need to be Aligned for Proper Device Operation) PLL Controller 2 Divider Change Register 0x01C4 0D44 DCHANGE (Indicates if SYSCLK Divide Ratio has Been Modified) 0x01C4 0D48 CKEN PLL Controller 2 Clock Enable Register 0x01C4 0D4C CKSTAT PLL Controller 2 Clock Status Register (For All Clocks Except SYSCLKx) Copyright © 2006–2010, Texas Instruments Incorporated Peripheral and Electrical Specifications 109 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 |
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